4 Commits

Author SHA1 Message Date
b2e4f9710d refactor(kernel): align GPIO pin layout with the reference listener
All checks were successful
Build kernel module / build (1:6.12.93-1+rpt1, bookworm) (pull_request) Successful in 1m1s
Build kernel module / build (1:6.18.34-1+rpt1, trixie) (pull_request) Successful in 1m8s
Build kernel module / package (pull_request) Successful in 29s
Build kernel module / release (pull_request) Has been skipped
Adopt the confirmed-working reference's pin assignment so the module runs
on that proven wiring: DATA=BCM2 (pin 3), CLK=BCM3 (pin 5), ATN=BCM4
(pin 7). RESET is kept and relocated to BCM17 (pin 11), the pin freed by
moving CLK. All five GPIOs stay in bank 0, so the direct-register hot
path and ATN IRQ are unchanged -- only the IEC_GPIO_* defines, the
device-tree overlay, and the docs/self-test move.

DATA/CLK now sit on the ARM I2C pins (GPIO2/3) with the SoC's fixed
~1.8k pull-ups; keep dtparam=i2c_arm off. The bare-board self-test
expectation changes from 0x15 to 0x0b accordingly.

Generated by Clanker
2026-06-20 16:09:10 +02:00
3135a2502b fix(kernel): Handle unreadable module files in selftest.sh
Improve error handling in module discovery by identifying unreadable
`.ko` files and providing detailed error messages. Suggest actions like
unzip or rebuild to resolve issues.
2026-06-20 05:13:48 +02:00
2aa5104812 feat(kernel): Improve selftest.sh module discovery and error handling
Enhance module selection process by validating vermagic against the running kernel. Add detailed error messages with suggestions for manual path overrides or rebuilding for the current kernel. Ensure robust fallback behavior and improve user guidance.
2026-06-20 04:53:40 +02:00
e0a78871ca feat(kernel): Add GPIO descriptor-based initialization and self-test script
Replace legacy gpio_to_desc() with GPIO descriptor resolution by chip label
and hardware number, ensuring compatibility with kernels using non-zero
gpiochip bases. Added `selftest.sh` for non-persistent module testing, which
performs a hardware self-test and verifies wiring before connecting the real
bus. Included a detailed README.md documenting the self-test process.
2026-06-19 00:23:45 +02:00