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2015d4c96e
| Author | SHA1 | Date | |
|---|---|---|---|
| 2015d4c96e | |||
| ec615dbb80 |
@ -16,6 +16,7 @@ the code in `kernel/` is built on.
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| Kernel↔userspace | Character device `/dev/iec0` + `kfifo` + wait queue (IEC ≤ 1000 B/s; relayfs not justified) | `iec_read`, `emit_record` |
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| `udelay` vs. poll | Poll-with-timeout for CLK transitions; `udelay` only for fixed delays (EOI ack 80 µs, EOI detect 250 µs) | `iec_timing.h`, `wait_clk` |
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| Sense-line reads | Debounced (glitch-filtered): a level change is believed only after it holds `IEC_DEBOUNCE_US` (5 µs); shorter pulses are rejected as noise. Mirrors a confirmed-working reference listener. Fast path is a single register read, so tight CLK polls stay cheap. ATN ISR + self-test stay **raw** | `iec_read_stable`, `db_*_asserted` |
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| DATA line control | All DATA assert/release in the worker + ATN ISR go through `iec_data_*_sync()` under `iec_data_lock`. The pin direction-flip is a read-modify-write of the shared `GPFSEL0`; without the lock the worker (one CPU) and the ATN ISR (another CPU on the quad-core Pi) could clobber each other's RMW. The release wrapper also **refuses to release while ATN is asserted**, so a ready-for-data release can never erase the ISR's presence acknowledge — the bug that caused intermittently missed LISTEN/UNLISTEN commands. init/exit/self-test keep the **raw** unconditional helpers | `iec_data_assert_sync`, `iec_data_release_sync`, `atn_isr` |
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| isolcpus / nohz_full | **Not** in the Phase-1 baseline. Add `isolcpus=3 nohz_full=3 rcu_nocbs=3 irqaffinity=0-2` only if Phase-2 bit-error rate > 1% | (boot cmdline) |
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| PREEMPT_RT | Stock kernel sufficient; RT is a last resort | — |
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| Module signing | Not required on stock RPi OS Bookworm | — |
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@ -129,6 +129,49 @@ static inline bool db_atn_asserted(void) { return iec_read_stable(IEC_GPIO_ATN
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static inline bool db_reset_asserted(void) { return iec_read_stable(IEC_GPIO_RESET, &db_reset) == 0; }
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static inline bool db_data_asserted(void) { return iec_read_stable(IEC_GPIO_DATA, &db_data) == 0; }
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/*
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* --- synchronized DATA line control --------------------------------------
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*
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* DATA is open-drain-emulated by flipping GPIO2's direction (iec_lines.h), and
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* that flip is a read-modify-write of the shared GPFSEL0 register. Two contexts
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* change DATA: the worker kthread (handshake) and the ATN falling-edge ISR
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* (presence acknowledge). On the quad-core Pi these can run on different CPUs at
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* the same time, so their RMWs can clobber each other -- e.g. the worker's RFD
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* release erasing the ISR's ATN ack, which makes the C64 see "device not
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* present" and drop the LISTEN/UNLISTEN command (the missed-command bug).
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*
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* iec_data_lock serializes every DATA change so the RMW is never split. In
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* addition, the release wrapper refuses to release while ATN is asserted: when
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* ATN is low the device must keep DATA low as the acknowledge, so a release the
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* worker was about to do for ready-for-data must not undo a just-arrived ack.
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* iec_atn_asserted() is the raw instantaneous read (matching the ISR's view);
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* the debounced db_atn_asserted() must NOT be used here.
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*
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* Only the worker/ISR hot path uses these. init/exit/selftest keep the raw
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* helpers: exit() must release the bus unconditionally, and selftest needs the
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* unconditional behaviour to probe the line.
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*/
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static DEFINE_SPINLOCK(iec_data_lock);
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static void iec_data_assert_sync(void)
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{
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unsigned long f;
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spin_lock_irqsave(&iec_data_lock, f);
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iec_data_assert();
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spin_unlock_irqrestore(&iec_data_lock, f);
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}
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static void iec_data_release_sync(void)
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{
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unsigned long f;
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spin_lock_irqsave(&iec_data_lock, f);
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if (!iec_atn_asserted())
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iec_data_release();
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spin_unlock_irqrestore(&iec_data_lock, f);
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}
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/* receive_byte() outcomes */
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enum iec_rx {
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IEC_RX_OK = 0, /* byte received */
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@ -204,7 +247,7 @@ static enum iec_rx receive_byte(u8 *out, bool *eoi, bool data_phase)
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rc = wait_clk(false /* released */, IEC_CLK_TIMEOUT_US, data_phase);
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if (rc != IEC_RX_OK)
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return rc;
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iec_data_release();
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iec_data_release_sync();
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local_irq_save(flags); /* IRQs off for the duration of the byte */
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@ -217,9 +260,9 @@ static enum iec_rx receive_byte(u8 *out, bool *eoi, bool data_phase)
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if (db_reset_asserted()) { rc = IEC_RX_RESET; goto out; }
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if (waited++ >= IEC_EOI_DETECT_US) {
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/* ack EOI: pull DATA low for Tei, then release */
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iec_data_assert();
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iec_data_assert_sync();
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udelay(IEC_EOI_ACK_HOLD_US);
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iec_data_release();
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iec_data_release_sync();
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*eoi = true;
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break;
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}
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@ -252,7 +295,7 @@ static enum iec_rx receive_byte(u8 *out, bool *eoi, bool data_phase)
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IEC_CLK_TIMEOUT_US, data_phase);
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if (rc != IEC_RX_OK)
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goto out;
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iec_data_assert();
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iec_data_assert_sync();
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*out = value;
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rc = IEC_RX_OK;
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@ -287,7 +330,7 @@ static void run_state_machine(void)
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enum iec_rx rc;
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if (kthread_should_stop()) {
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iec_data_release();
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iec_data_release_sync();
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return;
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}
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if (db_reset_asserted())
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@ -310,7 +353,7 @@ static void run_state_machine(void)
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/* ATN released */
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if (!addressed_listener) {
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emit_record(IEC_KIND_EVENT, IEC_EV_ATN_RELEASED, 0);
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iec_data_release();
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iec_data_release_sync();
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return; /* not our business -> IDLE */
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}
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@ -318,7 +361,7 @@ static void run_state_machine(void)
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emit_record(IEC_KIND_EVENT, IEC_EV_ATN_RELEASED, IEC_FLAG_ADDRESSED);
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for (;;) {
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if (kthread_should_stop()) {
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iec_data_release();
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iec_data_release_sync();
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return;
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}
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if (db_reset_asserted())
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@ -344,7 +387,7 @@ static void run_state_machine(void)
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reset:
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addressed_listener = false;
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iec_data_release();
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iec_data_release_sync();
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emit_record(IEC_KIND_EVENT, IEC_EV_RESET, 0);
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}
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@ -369,7 +412,7 @@ static int iec_worker(void *unused)
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static irqreturn_t atn_isr(int irq, void *dev)
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{
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if (iec_atn_asserted()) {
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iec_data_assert(); /* pull DATA low immediately (ack) */
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iec_data_assert_sync(); /* pull DATA low immediately (ack) */
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atomic_set(&iec_atn_pending, 1);
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wake_up_interruptible(&iec_work_wq);
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}
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