/* SPDX-License-Identifier: GPL-2.0 */ /* * iec_timing.h - starting timing constants for the listener handshake. * * Cross-referenced from the IEC spec, sd2iec empirical values, and ninepin / * raspbiec observed values. See the "Starting Constants Table" and ยง1.7 of * _research/pi-kernel-module-rt-gpio-2026-06-18.md. Tune in Phase 2 against a * real C64 / logic analyser. */ #ifndef _IEC_TIMING_H #define _IEC_TIMING_H /* Per-CLK-transition busy-poll timeout. Generous; abort the byte and report a * frame error if a CLK edge does not arrive within this window. Bounds the * IRQ-off interval at ~8 ms worst case (8 bits), ~200 us in the normal case. */ #define IEC_CLK_TIMEOUT_US 1000 /* EOI detection: after releasing DATA (ready-for-data), if CLK does not assert * within this window the talker is signalling EOI. Spec >= 200 us; sd2iec uses * 256 us. We use 250 us (+25% margin over spec). */ #define IEC_EOI_DETECT_US 250 /* EOI acknowledge hold: pull DATA low for this long to ack EOI. Spec (Tei) * >= 60 us; sd2iec uses 73 us (AVR instruction-calibrated). Pi A53 is faster; * 80 us gives margin. */ #define IEC_EOI_ACK_HOLD_US 80 /* Glitch filter window for sense-line reads. A level change is only believed * once it has held this long; a shorter pulse is treated as noise. Matches a * confirmed-working reference listener (5 us). sd2iec / the 1571 ROM * use a comparable few-microsecond debounce. Far shorter than a real IEC bit * (tens of us), so it never smears valid data. */ #define IEC_DEBOUNCE_US 5 /* Between-bytes minimum hold before the talker releases CLK for the next byte * (Tbb). We simply wait for the next CLK transition; this is documentary. */ #define IEC_BETWEEN_BYTES_US 100 /* * ATN response (Tat <= 1000 us) is NOT a udelay: it is performed by the ATN * falling-edge ISR pulling DATA low immediately (hardirq latency ~5-20 us on * the A53). Byte acknowledge (Tf <= 1000 us) is likewise immediate -- a single * GPIO write at the end of the IRQ-off bit loop. */ #endif /* _IEC_TIMING_H */