diff --git a/src/mon_m65/bsmon.s b/src/mon_m65/bsmon.s
index b9cfc229..d22f19f6 100644
--- a/src/mon_m65/bsmon.s
+++ b/src/mon_m65/bsmon.s
@@ -16,7 +16,8 @@
 ; * Register storage *
 ; ********************
 
-!addr Bank        =  2         ; $00 = C64 address, $FF = M65 flat address ; XXX adapt the implementation
+!addr Bank        =  2 ; XXX remove this        
+!addr Adr_Mode    =  2 ; $00 = C64 address, $80 = M65 flat address ; XXX adapt the implementation
 !addr PCH         =  3
 !addr PCL         =  4
 !addr SR          =  5
@@ -76,30 +77,7 @@
 Mon_Break
 ; *******
 
-         JSR  Print_Commands
-
-; pull BP, Z, Y, X, A,SR,PCL,PCH
-;       7  6  5  4  3  2  1  0
-
-         LDX  #7
-@loop    PLA
-         STA  PCH,X
-         DEX
-         BPL  @loop
-
-; decrement PC to point after BRK
-
-         LDA  PCL
-         BNE  @nopage
-         DEC  PCH
-@nopage  DEC  PCL
-
-         LDA  $011d
-         BBR7 Bank,@bank
-         LDA  $011f
-@bank    AND  #15
-         STA  Bank
-         BRA  Mon_Start
+         ; XXX implement Open ROMs version, connect it to BRK handler
 
 ; ******
 Mon_Call
@@ -468,6 +446,8 @@ Fetch
 Mon_Memory
 ; ********
 
+         LDA  #$00
+         STA  Adr_Mode
          JSR  Set_MODE_80
 
          JSR  Get_LAC           ; get 1st. parameter
@@ -1734,7 +1714,7 @@ Got_LAC
          DEC  Buf_Index
 
 ; *****
-Get_LAC
+Get_LAC ;
 ; *****
 
          JSR  Read_Number
diff --git a/src/zvm_m65/z80_instr_load_8bit.s b/src/zvm_m65/z80_instr_load_8bit.s
index ad7eddf5..ec3270f5 100644
--- a/src/zvm_m65/z80_instr_load_8bit.s
+++ b/src/zvm_m65/z80_instr_load_8bit.s
@@ -362,37 +362,44 @@ Z80_instr_7E:      ; LD A,(HL)
 Z80_instr_70:      ; LD (HL),B
 
 	lda REG_B
-	jmp (VEC_store_via_HL)
+	jsr (VEC_store_via_HL)
+	jmp ZVM_next
 
 Z80_instr_71:      ; LD (HL),C
 
 	lda REG_C
-	jmp (VEC_store_via_HL)
+	jsr (VEC_store_via_HL)
+	jmp ZVM_next
 
 Z80_instr_72:      ; LD (HL),D
 
 	lda REG_D
-	jmp (VEC_store_via_HL)
+	jsr (VEC_store_via_HL)
+	jmp ZVM_next
 
 Z80_instr_73:      ; LD (HL),E
 
 	lda REG_E
-	jmp (VEC_store_via_HL)
+	jsr (VEC_store_via_HL)
+	jmp ZVM_next
 
 Z80_instr_74:      ; LD (HL),H
 
 	lda REG_H
-	jmp (VEC_store_via_HL)
+	jsr (VEC_store_via_HL)
+	jmp ZVM_next
 
 Z80_instr_75:      ; LD (HL),L
 
 	lda REG_L
-	jmp (VEC_store_via_HL)
+	jsr (VEC_store_via_HL)
+	jmp ZVM_next
 
 Z80_instr_77:      ; LD (HL),A
 
 	lda REG_A
-	jmp (VEC_store_via_HL)
+	jsr (VEC_store_via_HL)
+	jmp ZVM_next
 
 ; XXX put here LD (IX+d),r family
 ; XXX put here LD (IY+d),r family
@@ -404,7 +411,8 @@ Z80_instr_77:      ; LD (HL),A
 Z80_instr_36:      ; LD (HL),n
 
 	jsr (VEC_fetch_value)
-	jmp (VEC_store_via_HL)
+	jsr (VEC_store_via_HL)
+	jmp ZVM_next
 
 ; XXX put here LD (IX+d),n family
 ; XXX put here LD (IY+d),n family
diff --git a/src/zvm_m65/z80_instr_math_8bit.s b/src/zvm_m65/z80_instr_math_8bit.s
index 87849057..f3377cc1 100644
--- a/src/zvm_m65/z80_instr_math_8bit.s
+++ b/src/zvm_m65/z80_instr_math_8bit.s
@@ -6,9 +6,179 @@
 ; XXX put ADD instructions here
 ; XXX put SUB instructions here
 ; XXX put SBC instructions here
-; XXX put AND instructions here
-; XXX put OR instructions here
-; XXX put XOR instructions here
+
+
+!macro Z80_AND_common_int {
+	lda REG_F
+	and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF - Z80_CF)
+	ora z80_ftable_AND, x
+	sta REG_F
+	jmp ZVM_next
+}
+
+!macro Z80_AND_common {
+	and REG_A
+	sta REG_A
+	tax
+
+	+Z80_AND_common_int
+}
+
+!macro Z80_AND_REGn .REGn {
+	lda .REGn
+	+Z80_AND_common
+}
+
+!macro Z80_AND_SELF {
+	ldx REG_A
+	+Z80_AND_common_int
+}
+
+!macro Z80_AND_VIA_HL {
+	jsr (VEC_fetch_via_HL)
+	+Z80_AND_common
+}
+
+!macro Z80_AND_n {
+	jsr (VEC_fetch_value)
+	+Z80_AND_common
+}
+
+!macro Z80_AND_VIA_IX_d {
+	jsr (VEC_fetch_via_IX_d)
+	+Z80_AND_common
+}
+
+!macro Z80_AND_VIA_IY_d {
+	jsr (VEC_fetch_via_IY_d)
+	+Z80_AND_common
+}
+
+Z80_instr_A0:      +Z80_AND_REGn REG_B                                         ; AND B
+Z80_instr_A1:      +Z80_AND_REGn REG_C                                         ; AND C
+Z80_instr_A2:      +Z80_AND_REGn REG_D                                         ; AND D
+Z80_instr_A3:      +Z80_AND_REGn REG_E                                         ; AND E
+Z80_instr_A4:      +Z80_AND_REGn REG_H                                         ; AND H
+Z80_instr_A5:      +Z80_AND_REGn REG_L                                         ; AND L
+Z80_instr_A6:      +Z80_AND_VIA_HL                                             ; AND (HL)
+Z80_instr_A7:      +Z80_AND_SELF                                               ; AND A
+Z80_instr_E6:      +Z80_AND_n                                                  ; AND n
+Z80_instr_DD_A6:   +Z80_AND_VIA_IX_d                                           ; AND (IX+d)
+Z80_instr_FD_A6:   +Z80_AND_VIA_IY_d                                           ; AND (IY+d)
+
+!macro Z80_OR_XOR_common_int {
+	lda REG_F
+	and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF - Z80_CF)
+	ora z80_ftable_OR_XOR, x
+	sta REG_F
+	jmp ZVM_next
+}
+
+!macro Z80_OR_common {
+	ora REG_A
+	sta REG_A
+	tax
+
+	+Z80_OR_XOR_common_int
+}
+
+!macro Z80_OR_REGn .REGn {
+	lda .REGn
+	+Z80_OR_common
+}
+
+!macro Z80_OR_SELF {
+	ldx REG_A
+	+Z80_OR_XOR_common_int
+}
+
+!macro Z80_OR_VIA_HL {
+	jsr (VEC_fetch_via_HL)
+	+Z80_OR_common
+}
+
+!macro Z80_OR_n {
+	jsr (VEC_fetch_value)
+	+Z80_OR_common
+}
+
+!macro Z80_OR_VIA_IX_d {
+	jsr (VEC_fetch_via_IX_d)
+	+Z80_OR_common
+}
+
+!macro Z80_OR_VIA_IY_d {
+	jsr (VEC_fetch_via_IY_d)
+	+Z80_OR_common
+}
+
+Z80_instr_B0:      +Z80_OR_REGn REG_B                                          ; OR B
+Z80_instr_B1:      +Z80_OR_REGn REG_C                                          ; OR C
+Z80_instr_B2:      +Z80_OR_REGn REG_D                                          ; OR D
+Z80_instr_B3:      +Z80_OR_REGn REG_E                                          ; OR E
+Z80_instr_B4:      +Z80_OR_REGn REG_H                                          ; OR H
+Z80_instr_B5:      +Z80_OR_REGn REG_L                                          ; OR L
+Z80_instr_B6:      +Z80_OR_VIA_HL                                              ; OR (HL)
+Z80_instr_B7:      +Z80_OR_SELF                                                ; OR A
+Z80_instr_F6:      +Z80_OR_n                                                   ; OR n
+Z80_instr_DD_B6:   +Z80_OR_VIA_IX_d                                            ; OR (IX+d)
+Z80_instr_FD_B6:   +Z80_OR_VIA_IY_d                                            ; OR (IY+d)
+
+!macro Z80_XOR_common {
+	eor REG_A
+	sta REG_A
+	tax
+
+	+Z80_OR_XOR_common_int
+}
+
+!macro Z80_XOR_REGn .REGn {
+	lda .REGn
+	+Z80_XOR_common
+}
+
+!macro Z80_XOR_SELF {
+	lda #$00
+	sta REG_A
+	lda REG_F
+	and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF - Z80_CF)
+	ora z80_ftable_OR_XOR
+	sta REG_F
+	jmp ZVM_next
+}
+
+!macro Z80_XOR_VIA_HL {
+	jsr (VEC_fetch_via_HL)
+	+Z80_XOR_common
+}
+
+!macro Z80_XOR_n {
+	jsr (VEC_fetch_value)
+	+Z80_XOR_common
+}
+
+!macro Z80_XOR_VIA_IX_d {
+	jsr (VEC_fetch_via_IX_d)
+	+Z80_XOR_common
+}
+
+!macro Z80_XOR_VIA_IY_d {
+	jsr (VEC_fetch_via_IY_d)
+	+Z80_XOR_common
+}
+
+Z80_instr_A8:      +Z80_XOR_REGn REG_B                                         ; XOR B
+Z80_instr_A9:      +Z80_XOR_REGn REG_C                                         ; XOR C
+Z80_instr_AA:      +Z80_XOR_REGn REG_D                                         ; XOR D
+Z80_instr_AB:      +Z80_XOR_REGn REG_E                                         ; XOR E
+Z80_instr_AC:      +Z80_XOR_REGn REG_H                                         ; XOR H
+Z80_instr_AD:      +Z80_XOR_REGn REG_L                                         ; XOR L
+Z80_instr_AE:      +Z80_XOR_VIA_HL                                             ; XOR (HL)
+Z80_instr_AF:      +Z80_XOR_SELF                                               ; XOR A
+Z80_instr_EE:      +Z80_XOR_n                                                  ; XOR n
+Z80_instr_DD_AE:   +Z80_XOR_VIA_IX_d                                           ; XOR (IX+d)
+Z80_instr_FD_AE:   +Z80_XOR_VIA_IY_d                                           ; XOR (IY+d)
+
 ; XXX put CP instructions here
 
 Z80_instr_04:      ; INC B
diff --git a/src/zvm_m65/z80_tables.s b/src/zvm_m65/z80_tables.s
index aaff7e1e..81c208bd 100644
--- a/src/zvm_m65/z80_tables.s
+++ b/src/zvm_m65/z80_tables.s
@@ -20,3 +20,11 @@ z80_ftable_INC:
 z80_ftable_DEC:
 
 	+PUT_Z80_FTABLE_DEC
+
+z80_ftable_AND:
+
+	+PUT_Z80_FTABLE_AND
+
+z80_ftable_OR_XOR:
+
+	+PUT_Z80_FTABLE_OR_XOR
diff --git a/src/zvm_m65/zvm_banking.s b/src/zvm_m65/zvm_banking.s
index a90bddc5..99464a3c 100644
--- a/src/zvm_m65/zvm_banking.s
+++ b/src/zvm_m65/zvm_banking.s
@@ -146,47 +146,14 @@ ZVM_fetch_via_nn_bank_0:
 ZVM_fetch_via_nn_bank_1:
 ZVM_store_stack_bank_0:
 ZVM_store_stack_bank_1:
-
-	; XXX
-	rts
-
 ZVM_store_via_HL_bank_0:
-
-	; XXX
-	jmp ZVM_next
-
 ZVM_store_via_HL_bank_1:
-
-	; XXX
-	jmp ZVM_next
-
 ZVM_store_via_IX_d_bank_0:
-
-	; XXX
-	jmp ZVM_next
-
 ZVM_store_via_IX_d_bank_1:
-
-	; XXX
-	jmp ZVM_next
-
 ZVM_store_via_IY_d_bank_0:
-
-	; XXX
-	jmp ZVM_next
-
 ZVM_store_via_IY_d_bank_1:
-
-	; XXX
-	jmp ZVM_next
-
 ZVM_store_via_nn_bank_0:
-
-	; XXX
-	jmp ZVM_next
-
 ZVM_store_via_nn_bank_1:
 
 	; XXX
-	jmp ZVM_next
-
+	rts
\ No newline at end of file
diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s
index 1bce3f8b..06d6d912 100644
--- a/src/zvm_m65/zvm_core.s
+++ b/src/zvm_m65/zvm_core.s
@@ -153,30 +153,6 @@ Z80_instr_9C:      ; SBC H
 Z80_instr_9D:      ; SBC L
 Z80_instr_9E:      ; SBC (HL)
 Z80_instr_9F:      ; SBC A
-Z80_instr_A0:      ; AND B
-Z80_instr_A1:      ; AND C
-Z80_instr_A2:      ; AND D
-Z80_instr_A3:      ; AND E
-Z80_instr_A4:      ; AND H
-Z80_instr_A5:      ; AND L
-Z80_instr_A6:      ; AND (HL)
-Z80_instr_A7:      ; AND A
-Z80_instr_A8:      ; XOR B
-Z80_instr_A9:      ; XOR C
-Z80_instr_AA:      ; XOR D
-Z80_instr_AB:      ; XOR E
-Z80_instr_AC:      ; XOR H
-Z80_instr_AD:      ; XOR L
-Z80_instr_AE:      ; XOR (HL)
-Z80_instr_AF:      ; XOR A
-Z80_instr_B0:      ; OR B
-Z80_instr_B1:      ; OR C
-Z80_instr_B2:      ; OR D
-Z80_instr_B3:      ; OR E
-Z80_instr_B4:      ; OR H
-Z80_instr_B5:      ; OR L
-Z80_instr_B6:      ; OR (HL)
-Z80_instr_B7:      ; OR A
 Z80_instr_B8:      ; CP B
 Z80_instr_B9:      ; CP C
 Z80_instr_BA:      ; CP D
@@ -208,15 +184,12 @@ Z80_instr_DF:      ; RST 18H
 Z80_instr_E0:      ; RET PO
 Z80_instr_E3:      ; EX (SP),HL
 Z80_instr_E4:      ; CALL PO,nn
-Z80_instr_E6:      ; AND n
 Z80_instr_E7:      ; RST 20H
 Z80_instr_E8:      ; RET PE
 Z80_instr_EC:      ; CALL PE,nn
-Z80_instr_EE:      ; XOR n
 Z80_instr_EF:      ; RST 28H
 Z80_instr_F0:      ; RET P
 Z80_instr_F4:      ; CALL P,nn
-Z80_instr_F6:      ; OR n
 Z80_instr_F7:      ; RST 30H
 Z80_instr_F8:      ; RET M
 Z80_instr_F9:      ; LD SP,HL
@@ -304,9 +277,6 @@ Z80_instr_DD_86:   ; ADD A,(IX+d)
 Z80_instr_DD_8E:   ; ADC A,(IX+d)
 Z80_instr_DD_96:   ; SUB (IX+d)
 Z80_instr_DD_9E:   ; SBC (IX+d)
-Z80_instr_DD_A6:   ; AND (IX+d)
-Z80_instr_DD_AE:   ; XOR (IX+d)
-Z80_instr_DD_B6:   ; OR (IX+d)
 Z80_instr_DD_BE:   ; CP (IX+d)
 Z80_instr_DD_E3:   ; EX (SP),IX
 Z80_instr_DD_F9:   ; LD SP,IX
@@ -384,9 +354,6 @@ Z80_instr_FD_86:   ; ADD A,(IY+d)
 Z80_instr_FD_8E:   ; ADC A,(IY+d)
 Z80_instr_FD_96:   ; SUB (IY+d)
 Z80_instr_FD_9E:   ; SBC (IY+d)
-Z80_instr_FD_A6:   ; AND (IY+d)
-Z80_instr_FD_AE:   ; XOR (IY+d)
-Z80_instr_FD_B6:   ; OR (IY+d)
 Z80_instr_FD_BE:   ; CP (IY+d)
 Z80_instr_FD_E3:   ; EX (SP),IY
 Z80_instr_FD_F9:   ; LD SP,IY
diff --git a/tools/generate_z80_tables.cc b/tools/generate_z80_tables.cc
index bf0d7f7a..91c01d0b 100644
--- a/tools/generate_z80_tables.cc
+++ b/tools/generate_z80_tables.cc
@@ -159,7 +159,7 @@ std::string generateIncTable(void)
 std::string generateDecTable(void)
 {
 	std::stringstream outStr;
-	outStr << "!macro PUT_Z80_FTABLE_DEC {\n" << std::hex << std::setw(2) << std::setfill('0');
+	outStr << "!macro PUT_Z80_FTABLE_DEC {\n";
 
 	for (uint16_t idx = 0; idx < 0x100; idx++)
 	{
@@ -176,6 +176,40 @@ std::string generateDecTable(void)
 	return outStr.str() + "}\n\n\n";
 } 
 
+std::string generateAndTable(void)
+{
+	std::stringstream outStr;
+	outStr << "!macro PUT_Z80_FTABLE_AND {\n";
+
+	for (uint16_t idx = 0; idx < 0x100; idx++)
+	{
+		uint8_t flags = Z80_HF | GLOBAL_Parity[idx];
+		if (idx >= 0x80) flags |= Z80_SF; // for negative result
+		if (idx == 0)    flags |= Z80_ZF; // for result equal 0
+
+		outStr << "\t!byte $" << std::hex << std::setw(2) << std::setfill('0') << int(flags) << "\n";
+	}
+
+	return outStr.str() + "}\n\n\n";
+}
+
+std::string generateOrXorTable(void)
+{
+	std::stringstream outStr;
+	outStr << "!macro PUT_Z80_FTABLE_OR_XOR {\n";
+
+	for (uint16_t idx = 0; idx < 0x100; idx++)
+	{
+		uint8_t flags = GLOBAL_Parity[idx];
+		if (idx >= 0x80) flags |= Z80_SF; // for negative result
+		if (idx == 0)    flags |= Z80_ZF; // for result equal 0
+
+		outStr << "\t!byte $" << std::hex << std::setw(2) << std::setfill('0') << int(flags) << "\n";
+	}
+
+	return outStr.str() + "}\n\n\n";
+} 
+
 std::string generateDaaTables()
 {
 	std::string outStr;
@@ -209,6 +243,8 @@ void writeTables()
 	outFile << generateDisplacementTable();
 	outFile << generateIncTable();
 	outFile << generateDecTable();
+	outFile << generateAndTable();
+	outFile << generateOrXorTable();
 	outFile << generateDaaTables();
 
 	// XXX