diff --git a/src/zvm_m65/,aliases_zvm.s b/src/zvm_m65/,aliases_zvm.s index cbae9086..c4a1d9ed 100644 --- a/src/zvm_m65/,aliases_zvm.s +++ b/src/zvm_m65/,aliases_zvm.s @@ -47,6 +47,6 @@ !set Z80_HF = %00010000 ; half carry !set Z80_XF = %00001000 ; bit 3 result !set Z80_PF = %00000100 ; parity -!set Z80_OF = %00000100 ; overflow -!set Z80_AF = %00000010 ; add/subtract +!set Z80_VF = %00000100 ; overflow +!set Z80_NF = %00000010 ; subtract !set Z80_CF = %00000001 ; carry diff --git a/src/zvm_m65/z80_bit.s b/src/zvm_m65/z80_bit.s index 9f127d3d..f94be83b 100644 --- a/src/zvm_m65/z80_bit.s +++ b/src/zvm_m65/z80_bit.s @@ -2,3 +2,1077 @@ ; ; Z80 bit set/reset/test instructions ; + +; XXX put BIT instructions here + +Z80_instr_CB_C0: ; SET 0,B + + lda REG_B + ora #%00000001 + sta REG_B + rts + +Z80_instr_CB_C1: ; SET 0,C + + lda REG_C + ora #%00000001 + sta REG_C + rts + +Z80_instr_CB_C2: ; SET 0,D + + lda REG_D + ora #%00000001 + sta REG_D + rts + +Z80_instr_CB_C3: ; SET 0,E + + lda REG_E + ora #%00000001 + sta REG_E + rts + +Z80_instr_CB_C4: ; SET 0,H + + lda REG_H + ora #%00000001 + sta REG_H + rts + +Z80_instr_CB_C5: ; SET 0,L + + lda REG_L + ora #%00000001 + sta REG_L + rts + +Z80_instr_CB_C7: ; SET 0,A + + lda REG_A + ora #%00000001 + sta REG_A + rts + +Z80_instr_CB_C8: ; SET 1,B + + lda REG_B + ora #%00000010 + sta REG_B + rts + +Z80_instr_CB_C9: ; SET 1, + + lda REG_C + ora #%00000010 + sta REG_C + rts + +Z80_instr_CB_CA: ; SET 1,D + + lda REG_D + ora #%00000010 + sta REG_D + rts + +Z80_instr_CB_CB: ; SET 1,E + + lda REG_E + ora #%00000010 + sta REG_E + rts + +Z80_instr_CB_CC: ; SET 1,H + + lda REG_H + ora #%00000010 + sta REG_H + rts + +Z80_instr_CB_CD: ; SET 1,L + + lda REG_L + ora #%00000010 + sta REG_L + rts + +Z80_instr_CB_CF: ; SET 1,A + + lda REG_A + ora #%00000010 + sta REG_A + rts + +Z80_instr_CB_D0: ; SET 2,B + + lda REG_B + ora #%00000100 + sta REG_B + rts + +Z80_instr_CB_D1: ; SET 2,C + + lda REG_C + ora #%00000100 + sta REG_C + rts + +Z80_instr_CB_D2: ; SET 2,D + + lda REG_D + ora #%00000100 + sta REG_D + rts + +Z80_instr_CB_D3: ; SET 2,E + + lda REG_E + ora #%00000100 + sta REG_E + rts + +Z80_instr_CB_D4: ; SET 2,H + + lda REG_H + ora #%00000100 + sta REG_H + rts + +Z80_instr_CB_D5: ; SET 2,L + + lda REG_L + ora #%00000100 + sta REG_L + rts + +Z80_instr_CB_D7: ; SET 2,A + + lda REG_A + ora #%00000100 + sta REG_A + rts + +Z80_instr_CB_D8: ; SET 3,B + + lda REG_B + ora #%00001000 + sta REG_B + rts + +Z80_instr_CB_D9: ; SET 3,C + + lda REG_C + ora #%00001000 + sta REG_C + rts + +Z80_instr_CB_DA: ; SET 3,D + + lda REG_D + ora #%00001000 + sta REG_D + rts + +Z80_instr_CB_DB: ; SET 3,E + + lda REG_E + ora #%00001000 + sta REG_E + rts + +Z80_instr_CB_DC: ; SET 3,H + + lda REG_H + ora #%00001000 + sta REG_H + rts + +Z80_instr_CB_DD: ; SET 3,L + + lda REG_L + ora #%00001000 + sta REG_L + rts + +Z80_instr_CB_DF: ; SET 3,A + + lda REG_A + ora #%00001000 + sta REG_A + rts + +Z80_instr_CB_E0: ; SET 4,B + + lda REG_B + ora #%00010000 + sta REG_B + rts + +Z80_instr_CB_E1: ; SET 4,C + + lda REG_C + ora #%00010000 + sta REG_C + rts + +Z80_instr_CB_E2: ; SET 4,D + + lda REG_D + ora #%00010000 + sta REG_D + rts + +Z80_instr_CB_E3: ; SET 4,E + + lda REG_E + ora #%00010000 + sta REG_E + rts + +Z80_instr_CB_E4: ; SET 4,H + + lda REG_H + ora #%00010000 + sta REG_H + rts + +Z80_instr_CB_E5: ; SET 4,L + + lda REG_L + ora #%00010000 + sta REG_L + rts + +Z80_instr_CB_E7: ; SET 4,A + + lda REG_A + ora #%00010000 + sta REG_A + rts + +Z80_instr_CB_E8: ; SET 5,B + + lda REG_B + ora #%00100000 + sta REG_B + rts + +Z80_instr_CB_E9: ; SET 5,C + + lda REG_C + ora #%00100000 + sta REG_C + rts + +Z80_instr_CB_EA: ; SET 5,D + + lda REG_D + ora #%00100000 + sta REG_D + rts + +Z80_instr_CB_EB: ; SET 5,E + + lda REG_E + ora #%00100000 + sta REG_E + rts + +Z80_instr_CB_EC: ; SET 5,H + + lda REG_H + ora #%00100000 + sta REG_H + rts + +Z80_instr_CB_ED: ; SET 5,L + + lda REG_L + ora #%00100000 + sta REG_L + rts + +Z80_instr_CB_EF: ; SET 5,A + + lda REG_A + ora #%00100000 + sta REG_A + rts + +Z80_instr_CB_F0: ; SET 6,B + + lda REG_B + ora #%01000000 + sta REG_B + rts + +Z80_instr_CB_F1: ; SET 6,C + + lda REG_C + ora #%01000000 + sta REG_C + rts + +Z80_instr_CB_F2: ; SET 6,D + + lda REG_D + ora #%01000000 + sta REG_D + rts + +Z80_instr_CB_F3: ; SET 6,E + + lda REG_E + ora #%01000000 + sta REG_E + rts + +Z80_instr_CB_F4: ; SET 6,H + + lda REG_H + ora #%01000000 + sta REG_H + rts + +Z80_instr_CB_F5: ; SET 6,L + + lda REG_L + ora #%01000000 + sta REG_L + rts + +Z80_instr_CB_F7: ; SET 6,A + + lda REG_A + ora #%01000000 + sta REG_A + rts + +Z80_instr_CB_F8: ; SET 7,B + + lda REG_B + ora #%10000000 + sta REG_B + rts + +Z80_instr_CB_F9: ; SET 7,C + + lda REG_C + ora #%10000000 + sta REG_C + rts + +Z80_instr_CB_FA: ; SET 7,D + + lda REG_D + ora #%10000000 + sta REG_D + rts + +Z80_instr_CB_FB: ; SET 7,E + + lda REG_E + ora #%10000000 + sta REG_E + rts + +Z80_instr_CB_FC: ; SET 7,H + + lda REG_H + ora #%10000000 + sta REG_H + rts + +Z80_instr_CB_FD: ; SET 7,L + + lda REG_L + ora #%10000000 + sta REG_L + rts + +Z80_instr_CB_FF: ; SET 7,A + + lda REG_A + ora #%10000000 + sta REG_A + rts + +Z80_instr_CB_C6: ; SET 0,(HL) + + jsr (VEC_fetch_via_HL) + ora #%00000001 + jmp ZVM_store_back + +Z80_instr_CB_CE: ; SET 1,(HL) + + jsr (VEC_fetch_via_HL) + ora #%00000010 + jmp ZVM_store_back + +Z80_instr_CB_D6: ; SET 2,(HL) + + jsr (VEC_fetch_via_HL) + ora #%00000100 + jmp ZVM_store_back + +Z80_instr_CB_DE: ; SET 3,(HL) + + jsr (VEC_fetch_via_HL) + ora #%00001000 + jmp ZVM_store_back + +Z80_instr_CB_E6: ; SET 4,(HL) + + jsr (VEC_fetch_via_HL) + ora #%00010000 + jmp ZVM_store_back + +Z80_instr_CB_EE: ; SET 5,(HL) + + jsr (VEC_fetch_via_HL) + ora #%00100000 + jmp ZVM_store_back + +Z80_instr_CB_F6: ; SET 6,(HL) + + jsr (VEC_fetch_via_HL) + ora #%01000000 + jmp ZVM_store_back + +Z80_instr_CB_FE: ; SET 7,(HL) + + jsr (VEC_fetch_via_HL) + ora #%10000000 + jmp ZVM_store_back + +Z80_instr_DDCB_C6: ; SET 0,(IX+d) + + jsr (VEC_fetch_via_IX_d) + ora #%00000001 + jmp ZVM_store_back + +Z80_instr_DDCB_CE: ; SET 1,(IX+d) + + jsr (VEC_fetch_via_IX_d) + ora #%00000010 + jmp ZVM_store_back + +Z80_instr_DDCB_D6: ; SET 2,(IX+d) + + jsr (VEC_fetch_via_IX_d) + ora #%00000100 + jmp ZVM_store_back + +Z80_instr_DDCB_DE: ; SET 3,(IX+d) + + jsr (VEC_fetch_via_IX_d) + ora #%00001000 + jmp ZVM_store_back + +Z80_instr_DDCB_E6: ; SET 4,(IX+d) + + jsr (VEC_fetch_via_IX_d) + ora #%00010000 + jmp ZVM_store_back + +Z80_instr_DDCB_EE: ; SET 5,(IX+d) + + jsr (VEC_fetch_via_IX_d) + ora #%00100000 + jmp ZVM_store_back + +Z80_instr_DDCB_F6: ; SET 6,(IX+d) + + jsr (VEC_fetch_via_IX_d) + ora #%01000000 + jmp ZVM_store_back + +Z80_instr_DDCB_FE: ; SET 7,(IX+d) + + jsr (VEC_fetch_via_IX_d) + ora #%10000000 + jmp ZVM_store_back + +Z80_instr_FDCB_C6: ; SET 0,(IY+d) + + jsr (VEC_fetch_via_IY_d) + ora #%00000001 + jmp ZVM_store_back + +Z80_instr_FDCB_CE: ; SET 1,(IY+d) + + jsr (VEC_fetch_via_IY_d) + ora #%00000010 + jmp ZVM_store_back + +Z80_instr_FDCB_D6: ; SET 2,(IY+d) + + jsr (VEC_fetch_via_IY_d) + ora #%00000100 + jmp ZVM_store_back + +Z80_instr_FDCB_DE: ; SET 3,(IY+d) + + jsr (VEC_fetch_via_IY_d) + ora #%00001000 + jmp ZVM_store_back + +Z80_instr_FDCB_E6: ; SET 4,(IY+d) + + jsr (VEC_fetch_via_IY_d) + ora #%00010000 + jmp ZVM_store_back + +Z80_instr_FDCB_EE: ; SET 5,(IY+d) + + jsr (VEC_fetch_via_IY_d) + ora #%00100000 + jmp ZVM_store_back + +Z80_instr_FDCB_F6: ; SET 6,(IY+d) + + jsr (VEC_fetch_via_IY_d) + ora #%01000000 + jmp ZVM_store_back + +Z80_instr_FDCB_FE: ; SET 7,(IY+d) + + jsr (VEC_fetch_via_IY_d) + ora #%10000000 + jmp ZVM_store_back + +Z80_instr_CB_80: ; RES 0,B + + lda REG_B + and #%11111110 + sta REG_B + rts + +Z80_instr_CB_81: ; RES 0,C + + lda REG_C + and #%11111110 + sta REG_C + rts + +Z80_instr_CB_82: ; RES 0,D + + lda REG_D + and #%11111110 + sta REG_D + rts + +Z80_instr_CB_83: ; RES 0,E + + lda REG_E + and #%11111110 + sta REG_E + rts + +Z80_instr_CB_84: ; RES 0,H + + lda REG_H + and #%11111110 + sta REG_H + rts + +Z80_instr_CB_85: ; RES 0,L + + lda REG_L + and #%11111110 + sta REG_L + rts + +Z80_instr_CB_87: ; RES 0,A + + lda REG_A + and #%11111110 + sta REG_A + rts + +Z80_instr_CB_88: ; RES 1,B + + lda REG_B + and #%11111101 + sta REG_B + rts + +Z80_instr_CB_89: ; RES 1,C + + lda REG_C + and #%11111101 + sta REG_C + rts + +Z80_instr_CB_8A: ; RES 1,D + + lda REG_D + and #%11111101 + sta REG_D + rts + +Z80_instr_CB_8B: ; RES 1,E + + lda REG_E + and #%11111101 + sta REG_E + rts + +Z80_instr_CB_8C: ; RES 1,H + + lda REG_H + and #%11111101 + sta REG_H + rts + +Z80_instr_CB_8D: ; RES 1,L + + lda REG_L + and #%11111101 + sta REG_L + rts + +Z80_instr_CB_8F: ; RES 1,A + + lda REG_A + and #%11111101 + sta REG_A + rts + +Z80_instr_CB_90: ; RES 2,B + + lda REG_B + and #%11111011 + sta REG_B + rts + +Z80_instr_CB_91: ; RES 2,C + + lda REG_C + and #%11111011 + sta REG_C + rts + +Z80_instr_CB_92: ; RES 2,D + + lda REG_D + and #%11111011 + sta REG_D + rts + +Z80_instr_CB_93: ; RES 2,E + + lda REG_E + and #%11111011 + sta REG_E + rts + +Z80_instr_CB_94: ; RES 2,H + + lda REG_H + and #%11111011 + sta REG_H + rts + +Z80_instr_CB_95: ; RES 2,L + + lda REG_L + and #%11111011 + sta REG_L + rts + +Z80_instr_CB_97: ; RES 2,A + + lda REG_A + and #%11111011 + sta REG_A + rts + +Z80_instr_CB_98: ; RES 3,B + + lda REG_B + and #%11110111 + sta REG_B + rts + +Z80_instr_CB_99: ; RES 3,C + + lda REG_C + and #%11110111 + sta REG_C + rts + +Z80_instr_CB_9A: ; RES 3,D + + lda REG_D + and #%11110111 + sta REG_D + rts + +Z80_instr_CB_9B: ; RES 3,E + + lda REG_E + and #%11110111 + sta REG_E + rts + +Z80_instr_CB_9C: ; RES 3,H + + lda REG_H + and #%11110111 + sta REG_H + rts + +Z80_instr_CB_9D: ; RES 3,L + + lda REG_L + and #%11110111 + sta REG_L + rts + +Z80_instr_CB_9F: ; RES 3,A + + lda REG_A + and #%11110111 + sta REG_A + rts + +Z80_instr_CB_A0: ; RES 4,B + + lda REG_B + and #%11101111 + sta REG_B + rts + +Z80_instr_CB_A1: ; RES 4,C + + lda REG_C + and #%11101111 + sta REG_C + rts + +Z80_instr_CB_A2: ; RES 4,D + + lda REG_D + and #%11101111 + sta REG_D + rts + +Z80_instr_CB_A3: ; RES 4,E + + lda REG_E + and #%11101111 + sta REG_E + rts + +Z80_instr_CB_A4: ; RES 4,H + + lda REG_H + and #%11101111 + sta REG_H + rts + +Z80_instr_CB_A5: ; RES 4,L + + lda REG_L + and #%11101111 + sta REG_L + rts + +Z80_instr_CB_A7: ; RES 4,A + + lda REG_A + and #%11101111 + sta REG_A + rts + +Z80_instr_CB_A8: ; RES 5,B + + lda REG_B + and #%11011111 + sta REG_B + rts + +Z80_instr_CB_A9: ; RES 5,C + + lda REG_C + and #%11011111 + sta REG_C + rts + +Z80_instr_CB_AA: ; RES 5,D + + lda REG_D + and #%11011111 + sta REG_D + rts + +Z80_instr_CB_AB: ; RES 5,E + + lda REG_E + and #%11011111 + sta REG_E + rts + +Z80_instr_CB_AC: ; RES 5,H + + lda REG_H + and #%11011111 + sta REG_H + rts + +Z80_instr_CB_AD: ; RES 5,L + + lda REG_L + and #%11011111 + sta REG_L + rts + +Z80_instr_CB_AF: ; RES 5,A + + lda REG_A + and #%11011111 + sta REG_A + rts + +Z80_instr_CB_B0: ; RES 6,B + + lda REG_B + and #%10111111 + sta REG_B + rts + +Z80_instr_CB_B1: ; RES 6,C + + lda REG_C + and #%10111111 + sta REG_C + rts + +Z80_instr_CB_B2: ; RES 6,D + + lda REG_D + and #%10111111 + sta REG_D + rts + +Z80_instr_CB_B3: ; RES 6,E + + lda REG_E + and #%10111111 + sta REG_E + rts + +Z80_instr_CB_B4: ; RES 6,H + + lda REG_H + and #%10111111 + sta REG_H + rts + +Z80_instr_CB_B5: ; RES 6,L + + lda REG_L + and #%10111111 + sta REG_L + rts + +Z80_instr_CB_B7: ; RES 6,A + + lda REG_A + and #%10111111 + sta REG_A + rts + +Z80_instr_CB_B8: ; RES 7,B + + lda REG_B + and #%01111111 + sta REG_B + rts + +Z80_instr_CB_B9: ; RES 7,C + + lda REG_C + and #%01111111 + sta REG_C + rts + +Z80_instr_CB_BA: ; RES 7,D + + lda REG_D + and #%01111111 + sta REG_D + rts + +Z80_instr_CB_BB: ; RES 7,E + + lda REG_E + and #%01111111 + sta REG_E + rts + +Z80_instr_CB_BC: ; RES 7,H + + lda REG_H + and #%01111111 + sta REG_H + rts + +Z80_instr_CB_BD: ; RES 7,L + + lda REG_L + and #%01111111 + sta REG_L + rts + +Z80_instr_CB_BF: ; RES 7,A + + lda REG_A + and #%01111111 + sta REG_A + rts + +Z80_instr_CB_86: ; RES 0,(HL) + + jsr (VEC_fetch_via_HL) + and #%11111110 + jmp ZVM_store_back + +Z80_instr_CB_8E: ; RES 1,(HL) + + jsr (VEC_fetch_via_HL) + and #%11111101 + jmp ZVM_store_back + +Z80_instr_CB_96: ; RES 2,(HL) + + jsr (VEC_fetch_via_HL) + and #%11111011 + jmp ZVM_store_back + +Z80_instr_CB_9E: ; RES 3,(HL) + + jsr (VEC_fetch_via_HL) + and #%11110111 + jmp ZVM_store_back + +Z80_instr_CB_A6: ; RES 4,(HL) + + jsr (VEC_fetch_via_HL) + and #%11101111 + jmp ZVM_store_back + +Z80_instr_CB_AE: ; RES 5,(HL) + + jsr (VEC_fetch_via_HL) + and #%11011111 + jmp ZVM_store_back + +Z80_instr_CB_B6: ; RES 6,(HL) + + jsr (VEC_fetch_via_HL) + and #%10111111 + jmp ZVM_store_back + +Z80_instr_CB_BE: ; RES 7,(HL) + + jsr (VEC_fetch_via_HL) + and #%01111111 + jmp ZVM_store_back + +Z80_instr_DDCB_86: ; RES 0,(IX+d) + + jsr (VEC_fetch_via_IX_d) + and #%11111110 + jmp ZVM_store_back + +Z80_instr_DDCB_8E: ; RES 1,(IX+d) + + jsr (VEC_fetch_via_IX_d) + and #%11111101 + jmp ZVM_store_back + +Z80_instr_DDCB_96: ; RES 2,(IX+d) + + jsr (VEC_fetch_via_IX_d) + and #%11111011 + jmp ZVM_store_back + +Z80_instr_DDCB_9E: ; RES 3,(IX+d) + + jsr (VEC_fetch_via_IX_d) + and #%11110111 + jmp ZVM_store_back + +Z80_instr_DDCB_A6: ; RES 4,(IX+d) + + jsr (VEC_fetch_via_IX_d) + and #%11101111 + jmp ZVM_store_back + +Z80_instr_DDCB_AE: ; RES 5,(IX+d) + + jsr (VEC_fetch_via_IX_d) + and #%11011111 + jmp ZVM_store_back + +Z80_instr_DDCB_B6: ; RES 6,(IX+d) + + jsr (VEC_fetch_via_IX_d) + and #%10111111 + jmp ZVM_store_back + +Z80_instr_DDCB_BE: ; RES 7,(IX+d) + + jsr (VEC_fetch_via_IX_d) + and #%01111111 + jmp ZVM_store_back + +Z80_instr_FDCB_86: ; RES 0,(IY+d) + + jsr (VEC_fetch_via_IY_d) + and #%11111110 + jmp ZVM_store_back + +Z80_instr_FDCB_8E: ; RES 1,(IY+d) + + jsr (VEC_fetch_via_IY_d) + and #%11111101 + jmp ZVM_store_back + +Z80_instr_FDCB_96: ; RES 2,(IY+d) + + jsr (VEC_fetch_via_IY_d) + and #%11111011 + jmp ZVM_store_back + +Z80_instr_FDCB_9E: ; RES 3,(IY+d) + + jsr (VEC_fetch_via_IY_d) + and #%11110111 + jmp ZVM_store_back + +Z80_instr_FDCB_A6: ; RES 4,(IY+d) + + jsr (VEC_fetch_via_IY_d) + and #%11101111 + jmp ZVM_store_back + +Z80_instr_FDCB_AE: ; RES 5,(IY+d) + + jsr (VEC_fetch_via_IY_d) + and #%11011111 + jmp ZVM_store_back + +Z80_instr_FDCB_B6: ; RES 6,(IY+d) + + jsr (VEC_fetch_via_IY_d) + and #%10111111 + jmp ZVM_store_back + +Z80_instr_FDCB_BE: ; RES 7,(IY+d) + + jsr (VEC_fetch_via_IY_d) + and #%01111111 + jmp ZVM_store_back diff --git a/src/zvm_m65/z80_math_8bit.s b/src/zvm_m65/z80_math_8bit.s index a0f65d39..0be65960 100644 --- a/src/zvm_m65/z80_math_8bit.s +++ b/src/zvm_m65/z80_math_8bit.s @@ -3,1076 +3,160 @@ ; Z80 arithmetic instructions, 8 bit ; -; XXX put BIT instructions here +; XXX put ADD instructions here +; XXX put SUB instructions here +; XXX put SBC instructions here +; XXX put AND instructions here +; XXX put OR instructions here +; XXX put XOR instructions here +; XXX put CP instructions here -Z80_instr_CB_C0: ; SET 0,B +Z80_instr_04: ; INC B - lda REG_B - ora #%00000001 - sta REG_B + ldx REG_B + inc REG_B + bra Z80_common_INC + +Z80_instr_0C: ; INC C + + ldx REG_C + inc REG_C + bra Z80_common_INC + +Z80_instr_14: ; INC D + + ldx REG_D + inc REG_D + bra Z80_common_INC + +Z80_instr_1C: ; INC E + + ldx REG_E + inc REG_E + bra Z80_common_INC + +Z80_instr_24: ; INC H + + ldx REG_H + inc REG_H + bra Z80_common_INC + +Z80_instr_2C: ; INC L + + ldx REG_L + inc REG_L + bra Z80_common_INC + +Z80_instr_3C: ; INC A + + ldx REG_A + inc REG_A + + ; FALLTROUGH + +Z80_common_INC: + + lda REG_F + and #(0xFF - Z80_SF - Z80_ZF - Z80_HF - Z80_VF - Z80_NF) + ora z80_ftable_INC, x + sta REG_F rts -Z80_instr_CB_C1: ; SET 0,C - - lda REG_C - ora #%00000001 - sta REG_C - rts - -Z80_instr_CB_C2: ; SET 0,D - - lda REG_D - ora #%00000001 - sta REG_D - rts - -Z80_instr_CB_C3: ; SET 0,E - - lda REG_E - ora #%00000001 - sta REG_E - rts - -Z80_instr_CB_C4: ; SET 0,H - - lda REG_H - ora #%00000001 - sta REG_H - rts - -Z80_instr_CB_C5: ; SET 0,L - - lda REG_L - ora #%00000001 - sta REG_L - rts - -Z80_instr_CB_C7: ; SET 0,A - - lda REG_A - ora #%00000001 - sta REG_A - rts - -Z80_instr_CB_C8: ; SET 1,B - - lda REG_B - ora #%00000010 - sta REG_B - rts - -Z80_instr_CB_C9: ; SET 1, - - lda REG_C - ora #%00000010 - sta REG_C - rts - -Z80_instr_CB_CA: ; SET 1,D - - lda REG_D - ora #%00000010 - sta REG_D - rts - -Z80_instr_CB_CB: ; SET 1,E - - lda REG_E - ora #%00000010 - sta REG_E - rts - -Z80_instr_CB_CC: ; SET 1,H - - lda REG_H - ora #%00000010 - sta REG_H - rts - -Z80_instr_CB_CD: ; SET 1,L - - lda REG_L - ora #%00000010 - sta REG_L - rts - -Z80_instr_CB_CF: ; SET 1,A - - lda REG_A - ora #%00000010 - sta REG_A - rts - -Z80_instr_CB_D0: ; SET 2,B - - lda REG_B - ora #%00000100 - sta REG_B - rts - -Z80_instr_CB_D1: ; SET 2,C - - lda REG_C - ora #%00000100 - sta REG_C - rts - -Z80_instr_CB_D2: ; SET 2,D - - lda REG_D - ora #%00000100 - sta REG_D - rts - -Z80_instr_CB_D3: ; SET 2,E - - lda REG_E - ora #%00000100 - sta REG_E - rts - -Z80_instr_CB_D4: ; SET 2,H - - lda REG_H - ora #%00000100 - sta REG_H - rts - -Z80_instr_CB_D5: ; SET 2,L - - lda REG_L - ora #%00000100 - sta REG_L - rts - -Z80_instr_CB_D7: ; SET 2,A - - lda REG_A - ora #%00000100 - sta REG_A - rts - -Z80_instr_CB_D8: ; SET 3,B - - lda REG_B - ora #%00001000 - sta REG_B - rts - -Z80_instr_CB_D9: ; SET 3,C - - lda REG_C - ora #%00001000 - sta REG_C - rts - -Z80_instr_CB_DA: ; SET 3,D - - lda REG_D - ora #%00001000 - sta REG_D - rts - -Z80_instr_CB_DB: ; SET 3,E - - lda REG_E - ora #%00001000 - sta REG_E - rts - -Z80_instr_CB_DC: ; SET 3,H - - lda REG_H - ora #%00001000 - sta REG_H - rts - -Z80_instr_CB_DD: ; SET 3,L - - lda REG_L - ora #%00001000 - sta REG_L - rts - -Z80_instr_CB_DF: ; SET 3,A - - lda REG_A - ora #%00001000 - sta REG_A - rts - -Z80_instr_CB_E0: ; SET 4,B - - lda REG_B - ora #%00010000 - sta REG_B - rts - -Z80_instr_CB_E1: ; SET 4,C - - lda REG_C - ora #%00010000 - sta REG_C - rts - -Z80_instr_CB_E2: ; SET 4,D - - lda REG_D - ora #%00010000 - sta REG_D - rts - -Z80_instr_CB_E3: ; SET 4,E - - lda REG_E - ora #%00010000 - sta REG_E - rts - -Z80_instr_CB_E4: ; SET 4,H - - lda REG_H - ora #%00010000 - sta REG_H - rts - -Z80_instr_CB_E5: ; SET 4,L - - lda REG_L - ora #%00010000 - sta REG_L - rts - -Z80_instr_CB_E7: ; SET 4,A - - lda REG_A - ora #%00010000 - sta REG_A - rts - -Z80_instr_CB_E8: ; SET 5,B - - lda REG_B - ora #%00100000 - sta REG_B - rts - -Z80_instr_CB_E9: ; SET 5,C - - lda REG_C - ora #%00100000 - sta REG_C - rts - -Z80_instr_CB_EA: ; SET 5,D - - lda REG_D - ora #%00100000 - sta REG_D - rts - -Z80_instr_CB_EB: ; SET 5,E - - lda REG_E - ora #%00100000 - sta REG_E - rts - -Z80_instr_CB_EC: ; SET 5,H - - lda REG_H - ora #%00100000 - sta REG_H - rts - -Z80_instr_CB_ED: ; SET 5,L - - lda REG_L - ora #%00100000 - sta REG_L - rts - -Z80_instr_CB_EF: ; SET 5,A - - lda REG_A - ora #%00100000 - sta REG_A - rts - -Z80_instr_CB_F0: ; SET 6,B - - lda REG_B - ora #%01000000 - sta REG_B - rts - -Z80_instr_CB_F1: ; SET 6,C - - lda REG_C - ora #%01000000 - sta REG_C - rts - -Z80_instr_CB_F2: ; SET 6,D - - lda REG_D - ora #%01000000 - sta REG_D - rts - -Z80_instr_CB_F3: ; SET 6,E - - lda REG_E - ora #%01000000 - sta REG_E - rts - -Z80_instr_CB_F4: ; SET 6,H - - lda REG_H - ora #%01000000 - sta REG_H - rts - -Z80_instr_CB_F5: ; SET 6,L - - lda REG_L - ora #%01000000 - sta REG_L - rts - -Z80_instr_CB_F7: ; SET 6,A - - lda REG_A - ora #%01000000 - sta REG_A - rts - -Z80_instr_CB_F8: ; SET 7,B - - lda REG_B - ora #%10000000 - sta REG_B - rts - -Z80_instr_CB_F9: ; SET 7,C - - lda REG_C - ora #%10000000 - sta REG_C - rts - -Z80_instr_CB_FA: ; SET 7,D - - lda REG_D - ora #%10000000 - sta REG_D - rts - -Z80_instr_CB_FB: ; SET 7,E - - lda REG_E - ora #%10000000 - sta REG_E - rts - -Z80_instr_CB_FC: ; SET 7,H - - lda REG_H - ora #%10000000 - sta REG_H - rts - -Z80_instr_CB_FD: ; SET 7,L - - lda REG_L - ora #%10000000 - sta REG_L - rts - -Z80_instr_CB_FF: ; SET 7,A - - lda REG_A - ora #%10000000 - sta REG_A - rts - -Z80_instr_CB_C6: ; SET 0,(HL) +Z80_instr_34: ; INC (HL) jsr (VEC_fetch_via_HL) - ora #%00000001 - jmp ZVM_store_back + tax + inc + jsr ZVM_store_back + bra Z80_common_INC -Z80_instr_CB_CE: ; SET 1,(HL) +Z80_instr_DD_34: ; INC (IX+d) + + jsr (VEC_fetch_via_IX_d) + tax + inc + jsr ZVM_store_back + bra Z80_common_INC + +Z80_instr_FD_34: ; INC (IY+d) + + jsr (VEC_fetch_via_IY_d) + tax + inc + jsr ZVM_store_back + bra Z80_common_INC + +Z80_instr_05: ; DEC B + + ldx REG_B + dec REG_B + bra Z80_common_DEC + +Z80_instr_0D: ; DEC C + + ldx REG_C + dec REG_C + bra Z80_common_DEC + +Z80_instr_15: ; DEC D + + ldx REG_D + dec REG_D + bra Z80_common_DEC + +Z80_instr_1D: ; DEC E + + ldx REG_E + dec REG_E + bra Z80_common_DEC + +Z80_instr_25: ; DEC H + + ldx REG_H + dec REG_H + bra Z80_common_DEC + +Z80_instr_2D: ; DEC L + + ldx REG_L + dec REG_L + bra Z80_common_DEC + +Z80_instr_3D: ; DEC A + + ldx REG_A + dec REG_A + + ; FALLTROUGH + +Z80_common_DEC: + + lda REG_F + and #(0xFF - Z80_SF - Z80_ZF - Z80_HF - Z80_VF - Z80_NF) + ora z80_ftable_DEC, x + sta REG_F + rts + +Z80_instr_35: ; DEC (HL) jsr (VEC_fetch_via_HL) - ora #%00000010 - jmp ZVM_store_back + tax + dec + jsr ZVM_store_back + bra Z80_common_DEC -Z80_instr_CB_D6: ; SET 2,(HL) - - jsr (VEC_fetch_via_HL) - ora #%00000100 - jmp ZVM_store_back - -Z80_instr_CB_DE: ; SET 3,(HL) - - jsr (VEC_fetch_via_HL) - ora #%00001000 - jmp ZVM_store_back - -Z80_instr_CB_E6: ; SET 4,(HL) - - jsr (VEC_fetch_via_HL) - ora #%00010000 - jmp ZVM_store_back - -Z80_instr_CB_EE: ; SET 5,(HL) - - jsr (VEC_fetch_via_HL) - ora #%00100000 - jmp ZVM_store_back - -Z80_instr_CB_F6: ; SET 6,(HL) - - jsr (VEC_fetch_via_HL) - ora #%01000000 - jmp ZVM_store_back - -Z80_instr_CB_FE: ; SET 7,(HL) - - jsr (VEC_fetch_via_HL) - ora #%10000000 - jmp ZVM_store_back - -Z80_instr_DDCB_C6: ; SET 0,(IX+d) +Z80_instr_DD_35: ; DEC (IX+d) jsr (VEC_fetch_via_IX_d) - ora #%00000001 - jmp ZVM_store_back + tax + dec + jsr ZVM_store_back + bra Z80_common_DEC -Z80_instr_DDCB_CE: ; SET 1,(IX+d) - - jsr (VEC_fetch_via_IX_d) - ora #%00000010 - jmp ZVM_store_back - -Z80_instr_DDCB_D6: ; SET 2,(IX+d) - - jsr (VEC_fetch_via_IX_d) - ora #%00000100 - jmp ZVM_store_back - -Z80_instr_DDCB_DE: ; SET 3,(IX+d) - - jsr (VEC_fetch_via_IX_d) - ora #%00001000 - jmp ZVM_store_back - -Z80_instr_DDCB_E6: ; SET 4,(IX+d) - - jsr (VEC_fetch_via_IX_d) - ora #%00010000 - jmp ZVM_store_back - -Z80_instr_DDCB_EE: ; SET 5,(IX+d) - - jsr (VEC_fetch_via_IX_d) - ora #%00100000 - jmp ZVM_store_back - -Z80_instr_DDCB_F6: ; SET 6,(IX+d) - - jsr (VEC_fetch_via_IX_d) - ora #%01000000 - jmp ZVM_store_back - -Z80_instr_DDCB_FE: ; SET 7,(IX+d) - - jsr (VEC_fetch_via_IX_d) - ora #%10000000 - jmp ZVM_store_back - -Z80_instr_FDCB_C6: ; SET 0,(IY+d) +Z80_instr_FD_35: ; DEC (IY+d) jsr (VEC_fetch_via_IY_d) - ora #%00000001 - jmp ZVM_store_back - -Z80_instr_FDCB_CE: ; SET 1,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00000010 - jmp ZVM_store_back - -Z80_instr_FDCB_D6: ; SET 2,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00000100 - jmp ZVM_store_back - -Z80_instr_FDCB_DE: ; SET 3,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00001000 - jmp ZVM_store_back - -Z80_instr_FDCB_E6: ; SET 4,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00010000 - jmp ZVM_store_back - -Z80_instr_FDCB_EE: ; SET 5,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00100000 - jmp ZVM_store_back - -Z80_instr_FDCB_F6: ; SET 6,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%01000000 - jmp ZVM_store_back - -Z80_instr_FDCB_FE: ; SET 7,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%10000000 - jmp ZVM_store_back - -Z80_instr_CB_80: ; RES 0,B - - lda REG_B - and #%11111110 - sta REG_B - rts - -Z80_instr_CB_81: ; RES 0,C - - lda REG_C - and #%11111110 - sta REG_C - rts - -Z80_instr_CB_82: ; RES 0,D - - lda REG_D - and #%11111110 - sta REG_D - rts - -Z80_instr_CB_83: ; RES 0,E - - lda REG_E - and #%11111110 - sta REG_E - rts - -Z80_instr_CB_84: ; RES 0,H - - lda REG_H - and #%11111110 - sta REG_H - rts - -Z80_instr_CB_85: ; RES 0,L - - lda REG_L - and #%11111110 - sta REG_L - rts - -Z80_instr_CB_87: ; RES 0,A - - lda REG_A - and #%11111110 - sta REG_A - rts - -Z80_instr_CB_88: ; RES 1,B - - lda REG_B - and #%11111101 - sta REG_B - rts - -Z80_instr_CB_89: ; RES 1,C - - lda REG_C - and #%11111101 - sta REG_C - rts - -Z80_instr_CB_8A: ; RES 1,D - - lda REG_D - and #%11111101 - sta REG_D - rts - -Z80_instr_CB_8B: ; RES 1,E - - lda REG_E - and #%11111101 - sta REG_E - rts - -Z80_instr_CB_8C: ; RES 1,H - - lda REG_H - and #%11111101 - sta REG_H - rts - -Z80_instr_CB_8D: ; RES 1,L - - lda REG_L - and #%11111101 - sta REG_L - rts - -Z80_instr_CB_8F: ; RES 1,A - - lda REG_A - and #%11111101 - sta REG_A - rts - -Z80_instr_CB_90: ; RES 2,B - - lda REG_B - and #%11111011 - sta REG_B - rts - -Z80_instr_CB_91: ; RES 2,C - - lda REG_C - and #%11111011 - sta REG_C - rts - -Z80_instr_CB_92: ; RES 2,D - - lda REG_D - and #%11111011 - sta REG_D - rts - -Z80_instr_CB_93: ; RES 2,E - - lda REG_E - and #%11111011 - sta REG_E - rts - -Z80_instr_CB_94: ; RES 2,H - - lda REG_H - and #%11111011 - sta REG_H - rts - -Z80_instr_CB_95: ; RES 2,L - - lda REG_L - and #%11111011 - sta REG_L - rts - -Z80_instr_CB_97: ; RES 2,A - - lda REG_A - and #%11111011 - sta REG_A - rts - -Z80_instr_CB_98: ; RES 3,B - - lda REG_B - and #%11110111 - sta REG_B - rts - -Z80_instr_CB_99: ; RES 3,C - - lda REG_C - and #%11110111 - sta REG_C - rts - -Z80_instr_CB_9A: ; RES 3,D - - lda REG_D - and #%11110111 - sta REG_D - rts - -Z80_instr_CB_9B: ; RES 3,E - - lda REG_E - and #%11110111 - sta REG_E - rts - -Z80_instr_CB_9C: ; RES 3,H - - lda REG_H - and #%11110111 - sta REG_H - rts - -Z80_instr_CB_9D: ; RES 3,L - - lda REG_L - and #%11110111 - sta REG_L - rts - -Z80_instr_CB_9F: ; RES 3,A - - lda REG_A - and #%11110111 - sta REG_A - rts - -Z80_instr_CB_A0: ; RES 4,B - - lda REG_B - and #%11101111 - sta REG_B - rts - -Z80_instr_CB_A1: ; RES 4,C - - lda REG_C - and #%11101111 - sta REG_C - rts - -Z80_instr_CB_A2: ; RES 4,D - - lda REG_D - and #%11101111 - sta REG_D - rts - -Z80_instr_CB_A3: ; RES 4,E - - lda REG_E - and #%11101111 - sta REG_E - rts - -Z80_instr_CB_A4: ; RES 4,H - - lda REG_H - and #%11101111 - sta REG_H - rts - -Z80_instr_CB_A5: ; RES 4,L - - lda REG_L - and #%11101111 - sta REG_L - rts - -Z80_instr_CB_A7: ; RES 4,A - - lda REG_A - and #%11101111 - sta REG_A - rts - -Z80_instr_CB_A8: ; RES 5,B - - lda REG_B - and #%11011111 - sta REG_B - rts - -Z80_instr_CB_A9: ; RES 5,C - - lda REG_C - and #%11011111 - sta REG_C - rts - -Z80_instr_CB_AA: ; RES 5,D - - lda REG_D - and #%11011111 - sta REG_D - rts - -Z80_instr_CB_AB: ; RES 5,E - - lda REG_E - and #%11011111 - sta REG_E - rts - -Z80_instr_CB_AC: ; RES 5,H - - lda REG_H - and #%11011111 - sta REG_H - rts - -Z80_instr_CB_AD: ; RES 5,L - - lda REG_L - and #%11011111 - sta REG_L - rts - -Z80_instr_CB_AF: ; RES 5,A - - lda REG_A - and #%11011111 - sta REG_A - rts - -Z80_instr_CB_B0: ; RES 6,B - - lda REG_B - and #%10111111 - sta REG_B - rts - -Z80_instr_CB_B1: ; RES 6,C - - lda REG_C - and #%10111111 - sta REG_C - rts - -Z80_instr_CB_B2: ; RES 6,D - - lda REG_D - and #%10111111 - sta REG_D - rts - -Z80_instr_CB_B3: ; RES 6,E - - lda REG_E - and #%10111111 - sta REG_E - rts - -Z80_instr_CB_B4: ; RES 6,H - - lda REG_H - and #%10111111 - sta REG_H - rts - -Z80_instr_CB_B5: ; RES 6,L - - lda REG_L - and #%10111111 - sta REG_L - rts - -Z80_instr_CB_B7: ; RES 6,A - - lda REG_A - and #%10111111 - sta REG_A - rts - -Z80_instr_CB_B8: ; RES 7,B - - lda REG_B - and #%01111111 - sta REG_B - rts - -Z80_instr_CB_B9: ; RES 7,C - - lda REG_C - and #%01111111 - sta REG_C - rts - -Z80_instr_CB_BA: ; RES 7,D - - lda REG_D - and #%01111111 - sta REG_D - rts - -Z80_instr_CB_BB: ; RES 7,E - - lda REG_E - and #%01111111 - sta REG_E - rts - -Z80_instr_CB_BC: ; RES 7,H - - lda REG_H - and #%01111111 - sta REG_H - rts - -Z80_instr_CB_BD: ; RES 7,L - - lda REG_L - and #%01111111 - sta REG_L - rts - -Z80_instr_CB_BF: ; RES 7,A - - lda REG_A - and #%01111111 - sta REG_A - rts - -Z80_instr_CB_86: ; RES 0,(HL) - - jsr (VEC_fetch_via_HL) - and #%11111110 - jmp ZVM_store_back - -Z80_instr_CB_8E: ; RES 1,(HL) - - jsr (VEC_fetch_via_HL) - and #%11111101 - jmp ZVM_store_back - -Z80_instr_CB_96: ; RES 2,(HL) - - jsr (VEC_fetch_via_HL) - and #%11111011 - jmp ZVM_store_back - -Z80_instr_CB_9E: ; RES 3,(HL) - - jsr (VEC_fetch_via_HL) - and #%11110111 - jmp ZVM_store_back - -Z80_instr_CB_A6: ; RES 4,(HL) - - jsr (VEC_fetch_via_HL) - and #%11101111 - jmp ZVM_store_back - -Z80_instr_CB_AE: ; RES 5,(HL) - - jsr (VEC_fetch_via_HL) - and #%11011111 - jmp ZVM_store_back - -Z80_instr_CB_B6: ; RES 6,(HL) - - jsr (VEC_fetch_via_HL) - and #%10111111 - jmp ZVM_store_back - -Z80_instr_CB_BE: ; RES 7,(HL) - - jsr (VEC_fetch_via_HL) - and #%01111111 - jmp ZVM_store_back - -Z80_instr_DDCB_86: ; RES 0,(IX+d) - - jsr (VEC_fetch_via_IX_d) - and #%11111110 - jmp ZVM_store_back - -Z80_instr_DDCB_8E: ; RES 1,(IX+d) - - jsr (VEC_fetch_via_IX_d) - and #%11111101 - jmp ZVM_store_back - -Z80_instr_DDCB_96: ; RES 2,(IX+d) - - jsr (VEC_fetch_via_IX_d) - and #%11111011 - jmp ZVM_store_back - -Z80_instr_DDCB_9E: ; RES 3,(IX+d) - - jsr (VEC_fetch_via_IX_d) - and #%11110111 - jmp ZVM_store_back - -Z80_instr_DDCB_A6: ; RES 4,(IX+d) - - jsr (VEC_fetch_via_IX_d) - and #%11101111 - jmp ZVM_store_back - -Z80_instr_DDCB_AE: ; RES 5,(IX+d) - - jsr (VEC_fetch_via_IX_d) - and #%11011111 - jmp ZVM_store_back - -Z80_instr_DDCB_B6: ; RES 6,(IX+d) - - jsr (VEC_fetch_via_IX_d) - and #%10111111 - jmp ZVM_store_back - -Z80_instr_DDCB_BE: ; RES 7,(IX+d) - - jsr (VEC_fetch_via_IX_d) - and #%01111111 - jmp ZVM_store_back - -Z80_instr_FDCB_86: ; RES 0,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11111110 - jmp ZVM_store_back - -Z80_instr_FDCB_8E: ; RES 1,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11111101 - jmp ZVM_store_back - -Z80_instr_FDCB_96: ; RES 2,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11111011 - jmp ZVM_store_back - -Z80_instr_FDCB_9E: ; RES 3,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11110111 - jmp ZVM_store_back - -Z80_instr_FDCB_A6: ; RES 4,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11101111 - jmp ZVM_store_back - -Z80_instr_FDCB_AE: ; RES 5,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11011111 - jmp ZVM_store_back - -Z80_instr_FDCB_B6: ; RES 6,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%10111111 - jmp ZVM_store_back - -Z80_instr_FDCB_BE: ; RES 7,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%01111111 - jmp ZVM_store_back + tax + dec + jsr ZVM_store_back + bra Z80_common_DEC diff --git a/src/zvm_m65/z80_tables.s b/src/zvm_m65/z80_tables.s new file mode 100644 index 00000000..b31a2c64 --- /dev/null +++ b/src/zvm_m65/z80_tables.s @@ -0,0 +1,17 @@ + +; +; Z80 tables for quickly calculating instruction results +; + + +z80_ftable_parity: + + +PUT_Z80_FTABLE_PARITY + +z80_ftable_INC: + + +PUT_Z80_FTABLE_INC + +z80_ftable_DEC: + + +PUT_Z80_FTABLE_DEC diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s index dc3da620..5a38da18 100644 --- a/src/zvm_m65/zvm_core.s +++ b/src/zvm_m65/zvm_core.s @@ -101,56 +101,40 @@ ZVM_run: Z80_instr_01: ; LD BC,nn Z80_instr_02: ; LD (BC),A Z80_instr_03: ; INC BC -Z80_instr_04: ; INC B -Z80_instr_05: ; DEC B Z80_instr_07: ; RLCA Z80_instr_09: ; ADD HL,BC Z80_instr_0A: ; LD A,(BC) Z80_instr_0B: ; DEC BC -Z80_instr_0C: ; INC C -Z80_instr_0D: ; DEC C Z80_instr_0F: ; RRCA Z80_instr_10: ; DJNZ e Z80_instr_11: ; LD DE,nn Z80_instr_12: ; LD (DE),A Z80_instr_13: ; INC DE -Z80_instr_14: ; INC D -Z80_instr_15: ; DEC D Z80_instr_17: ; RLA Z80_instr_18: ; JR e Z80_instr_19: ; ADD HL,DE Z80_instr_1A: ; LD A,(DE) Z80_instr_1B: ; DEC DE -Z80_instr_1C: ; INC E -Z80_instr_1D: ; DEC E Z80_instr_1F: ; RRA Z80_instr_20: ; JR NZ,e Z80_instr_21: ; LD HL,nn Z80_instr_22: ; LD (nn),HL Z80_instr_23: ; INC HL -Z80_instr_24: ; INC H -Z80_instr_25: ; DEC H Z80_instr_27: ; DAA Z80_instr_28: ; JR Z,e Z80_instr_29: ; ADD HL,HL Z80_instr_2A: ; LD HL,(nn) Z80_instr_2B: ; DEC HL -Z80_instr_2C: ; INC L -Z80_instr_2D: ; DEC L Z80_instr_2F: ; CPL Z80_instr_30: ; JR NC,e Z80_instr_31: ; LD SP,nn Z80_instr_32: ; LD (nn),A Z80_instr_33: ; INC SP -Z80_instr_34: ; INC (HL) -Z80_instr_35: ; DEC (HL) Z80_instr_37: ; SCF Z80_instr_38: ; JR C,e Z80_instr_39: ; ADD HL,SP Z80_instr_3A: ; LD A,(nn) Z80_instr_3B: ; DEC SP -Z80_instr_3C: ; INC A -Z80_instr_3D: ; DEC A Z80_instr_3F: ; CCF Z80_instr_76: ; HALT Z80_instr_80: ; ADD A,B @@ -407,8 +391,6 @@ Z80_instr_DD_23: ; DEC IX Z80_instr_DD_29: ; ADD IX,IX Z80_instr_DD_2A: ; LD IX,(nn) Z80_instr_DD_2B: ; DEC IX -Z80_instr_DD_34: ; INC (IX+d) -Z80_instr_DD_35: ; DEC (IX+d) Z80_instr_DD_39: ; ADD IX,SP Z80_instr_DD_46: ; LD B,(IX+d) Z80_instr_DD_4E: ; LD C,(IX+d) @@ -502,8 +484,6 @@ Z80_instr_FD_23: ; INC IY Z80_instr_FD_29: ; ADD IY,IY Z80_instr_FD_2A: ; LD IY,(nn) Z80_instr_FD_2B: ; DEC IY -Z80_instr_FD_34: ; INC (IY+d) -Z80_instr_FD_35: ; DEC (IY+d) Z80_instr_FD_39: ; ADD IY,SP Z80_instr_FD_46: ; LD B,(IY+d) Z80_instr_FD_4E: ; LD C,(IY+d) diff --git a/tools/generate_z80_tables.cc b/tools/generate_z80_tables.cc index e78efae1..519c404f 100644 --- a/tools/generate_z80_tables.cc +++ b/tools/generate_z80_tables.cc @@ -10,6 +10,22 @@ #include #include +// +// Constants +// + +static const uint8_t Z80_SF = 0x80; // sign +static const uint8_t Z80_ZF = 0x40; // zero +static const uint8_t Z80_YF = 0x20; // bit 5 result +static const uint8_t Z80_HF = 0x10; // half carry +static const uint8_t Z80_XF = 0x08; // bit 3 result +static const uint8_t Z80_PF = 0x04; // parity +static const uint8_t Z80_VF = 0x04; // overflow +static const uint8_t Z80_NF = 0x02; // add/subtract +static const uint8_t Z80_CF = 0x01; // carry + + + // // Command line settings // @@ -59,7 +75,7 @@ void parseCommandLine(int argc, char **argv) std::string generateParityTable(void) { - std::string outStr = "!macro PUT_Z80_TABLE_PARITY {\n";; + std::string outStr = "!macro PUT_Z80_FTABLE_PARITY {\n"; for (uint16_t idx = 0; idx < 0x100; idx++) { @@ -89,7 +105,51 @@ std::string generateParityTable(void) } } - return outStr + "}\n\n\n";; + return outStr + "}\n\n\n"; +} + +std::string generateIncTable(void) +{ + std::stringstream outStr; + + outStr << "!macro PUT_Z80_FTABLE_INC {\n"; + + for (uint16_t idx = 0; idx < 0x100; idx++) + { + uint8_t flags = 0; + + if (idx >= 0x7F && idx != 0xFF) flags |= Z80_SF; // for negative result + if (idx == 0xFF) flags |= Z80_ZF; // for result equal 0 + if ((idx & 0x0F) == 0x0F) flags |= Z80_HF; + if (idx == 0x7F) flags |= Z80_VF; + + outStr << "\t!byte "; + outStr << std::hex << std::setw(2) << int(flags) << "\n"; + } + + return outStr.str() + "}\n\n\n"; +} + +std::string generateDecTable(void) +{ + std::stringstream outStr; + + outStr << "!macro PUT_Z80_FTABLE_DEC {\n"; + + for (uint16_t idx = 0; idx < 0x100; idx++) + { + uint8_t flags = Z80_NF; + + if (idx >= 0x81 || idx == 0x00) flags |= Z80_SF; // for negative result + if (idx == 0x01) flags |= Z80_ZF; // for result equal 0 + if ((idx & 0x0F) == 0x00) flags |= Z80_HF; + if (idx == 0x80) flags |= Z80_VF; + + outStr << "\t!byte "; + outStr << std::hex << std::setw(2) << int(flags) << "\n"; + } + + return outStr.str() + "}\n\n\n"; } std::string generateDaaTables() @@ -122,6 +182,8 @@ void writeTables() // Write tables outFile << generateParityTable(); + outFile << generateIncTable(); + outFile << generateDecTable(); outFile << generateDaaTables(); // XXX