diff --git a/c64/kernal/iec/iec_tx_byte.s b/c64/kernal/iec/iec_tx_byte.s
index 82cf41c0..6a978848 100644
--- a/c64/kernal/iec/iec_tx_byte.s
+++ b/c64/kernal/iec/iec_tx_byte.s
@@ -32,19 +32,12 @@ iec_tx_common:
 	;; Wait till all receivers are ready, they should all release DATA
 	jsr iec_wait_for_data_release
 
-	;; At this point a delay 256 usec or more is considered EOI - add waits if necessary
-	bcc +
-	jsr iec_wait100us
-	jsr iec_wait100us
-	jsr iec_wait60us
-
-	;; XXX waits above should be enough - why do we need more waits???
-	jsr iec_wait100us
-	jsr iec_wait100us
-	jsr iec_wait100us
-
-	;; Receiver should now acknowledge EOI by pulling data for at least 60 usec
-	jsr iec_wait60us
+	;; At this point a delay 256 usec or more is considered EOI,
+	;; receiver should now acknowledge it by pulling data for at least 60 usec
+	;; Keep the implementation as simple as possible: data should be released now
+	;; so wait until it's pushed and released again
+	
+	jsr iec_wait_for_data_pull
 	jsr iec_wait_for_data_release
 *
 	;; Pull CLK back to indicate that DATA is not valid, keep it for 60us
diff --git a/c64/kernal/iec/iec_wait100us.s b/c64/kernal/iec/iec_wait100us.s
deleted file mode 100644
index b3101685..00000000
--- a/c64/kernal/iec/iec_wait100us.s
+++ /dev/null
@@ -1,22 +0,0 @@
-
-iec_wait100us:	
-
-	;; Wait 100usec
-
-	;; PAL:
-	;; - CPU frequency 0.985248 MHz, we need to waste at least  99 cycles
-	;; NTSC:
-	;; - CPU frequency 1.022727 MHZ, we need to waste at least 103 cycles
-
-	;; Waste cycles in a loop
-
-	ldy #$12   ; 2 cycles
-*	dey        ; 2 cycles * 18
-	bpl -      ; 3 cycles * 17 + 2 cycles
-	rts        ; 6 cycles
-
-	;;   6 cycles JSR to routine, 
-    ;;  97 cycles routine with RTS
-    ;;   1 cycle to fetch next instruction
-    ;; ---
-    ;;  104 cycles