diff --git a/src/zvm_m65/,aliases_zvm.s b/src/zvm_m65/,aliases_zvm.s index f448259d..b7cd7ec5 100644 --- a/src/zvm_m65/,aliases_zvm.s +++ b/src/zvm_m65/,aliases_zvm.s @@ -26,7 +26,9 @@ !addr REG_R06 = $1B ; refresh counter, bits 0-6 (bit 7 is garbage) !addr REG_R7 = $1C ; refresh counter, bit 7 (bits 0-6 are 0's) -!addr ADDR_IXY_d = $1D ; 16-bit calculated address IX+d / IY+d XXX - important!!! +!addr PTR_IXY_d = $1D ; 16-bit calculated address IX+d / IY+d XXX - important!!! +!addr PTR_DATA = $1D ; data source address XXX is it OK to use the same one? + !addr REG_IFF1 = $1F ; interrupt flip-flop flag 1 !addr REG_IFF2 = $20 ; interrupt flip-flop flag 2 diff --git a/src/zvm_m65/z80_instr_bit.s b/src/zvm_m65/z80_instr_bit.s index e83b7772..6d381255 100644 --- a/src/zvm_m65/z80_instr_bit.s +++ b/src/zvm_m65/z80_instr_bit.s @@ -118,7 +118,7 @@ Z80_common_bitx_0: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF) ora #($00 + Z80_HF + Z80_ZF + Z80_PF) sta REG_F - rts + jmp ZVM_next Z80_common_bitx_1: @@ -126,7 +126,7 @@ Z80_common_bitx_1: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF - Z80_ZF - Z80_PF) ora #($00 + Z80_HF) sta REG_F - rts + jmp ZVM_next Z80_instr_CB_60: ; BIT 4,B @@ -242,7 +242,7 @@ Z80_common_bit3_0: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF) ora #($00 + Z80_HF + Z80_ZF + Z80_PF) sta REG_F - rts + jmp ZVM_next Z80_common_bit3_1: @@ -250,7 +250,7 @@ Z80_common_bit3_1: and #($FF - Z80_NF - Z80_YF - Z80_SF - Z80_ZF - Z80_PF) ora #($00 + Z80_HF + Z80_XF) sta REG_F - rts + jmp ZVM_next Z80_instr_CB_68: ; BIT 5,B @@ -295,7 +295,7 @@ Z80_common_bit5_0: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF) ora #($00 + Z80_HF + Z80_ZF + Z80_PF) sta REG_F - rts + jmp ZVM_next Z80_common_bit5_1: @@ -303,7 +303,7 @@ Z80_common_bit5_1: and #($FF - Z80_NF - Z80_XF - Z80_SF - Z80_ZF - Z80_PF) ora #($00 + Z80_HF + Z80_YF) sta REG_F - rts + jmp ZVM_next Z80_instr_CB_78: ; BIT 7,B @@ -347,7 +347,7 @@ Z80_common_bit7_0: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF) ora #($00 + Z80_HF + Z80_ZF + Z80_PF) sta REG_F - rts + jmp ZVM_next Z80_common_bit7_1: @@ -355,7 +355,7 @@ Z80_common_bit7_1: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_ZF - Z80_PF) ora #($00 + Z80_HF + Z80_SF) sta REG_F - rts + jmp ZVM_next ; bits taken from (HL) @@ -418,7 +418,7 @@ Z80_instr_CB_7E: ; BIT 7,(HL) and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_ZF - Z80_PF) ora #($00 + Z80_HF + Z80_SF) sta REG_F - rts + jmp ZVM_next Z80_common_bitHL_0: @@ -427,7 +427,7 @@ Z80_common_bitHL_0: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF) ora #($00 + Z80_HF + Z80_ZF + Z80_PF) sta REG_F - rts + jmp ZVM_next Z80_common_bitHL_1: @@ -436,7 +436,7 @@ Z80_common_bitHL_1: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF - Z80_ZF - Z80_PF) ora #($00 + Z80_HF) sta REG_F - rts + jmp ZVM_next ; bits taken from index register + displacement @@ -503,11 +503,11 @@ Z80_common_bitXY7_1: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_ZF - Z80_PF) ora #($00 + Z80_HF + Z80_SF) sta REG_F - lda ADDR_IXY_d+1 + lda PTR_IXY_d+1 and #(Z80_XF + Z80_YF) ora REG_F sta REG_F - rts + jmp ZVM_next Z80_common_bitXYx_0: @@ -515,11 +515,11 @@ Z80_common_bitXYx_0: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF) ora #($00 + Z80_HF + Z80_ZF + Z80_PF) sta REG_F - lda ADDR_IXY_d+1 + lda PTR_IXY_d+1 and #(Z80_XF + Z80_YF) ora REG_F sta REG_F - rts + jmp ZVM_next Z80_common_bitXYx_1: @@ -527,11 +527,11 @@ Z80_common_bitXYx_1: and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF - Z80_ZF - Z80_PF) ora #($00 + Z80_HF) sta REG_F - lda ADDR_IXY_d+1 + lda PTR_IXY_d+1 and #(Z80_XF + Z80_YF) ora REG_F sta REG_F - rts + jmp ZVM_next Z80_instr_FDCB_46: ; BIT 0,(IY+d) @@ -586,7 +586,7 @@ Z80_instr_FDCB_7E: ; BIT 7,(IY+d) jsr (VEC_fetch_via_IY_d) and #%10000000 - bne Z80_common_bitXY7_1 + +bne Z80_common_bitXY7_1 ; too far away for normal BNE bra Z80_common_bitXYx_0 ; SET, RES @@ -596,1069 +596,1069 @@ Z80_instr_CB_C0: ; SET 0,B lda REG_B ora #%00000001 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_C1: ; SET 0,C lda REG_C ora #%00000001 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_C2: ; SET 0,D lda REG_D ora #%00000001 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_C3: ; SET 0,E lda REG_E ora #%00000001 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_C4: ; SET 0,H lda REG_H ora #%00000001 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_C5: ; SET 0,L lda REG_L ora #%00000001 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_C7: ; SET 0,A lda REG_A ora #%00000001 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_C8: ; SET 1,B lda REG_B ora #%00000010 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_C9: ; SET 1, lda REG_C ora #%00000010 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_CA: ; SET 1,D lda REG_D ora #%00000010 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_CB: ; SET 1,E lda REG_E ora #%00000010 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_CC: ; SET 1,H lda REG_H ora #%00000010 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_CD: ; SET 1,L lda REG_L ora #%00000010 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_CF: ; SET 1,A lda REG_A ora #%00000010 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_D0: ; SET 2,B lda REG_B ora #%00000100 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_D1: ; SET 2,C lda REG_C ora #%00000100 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_D2: ; SET 2,D lda REG_D ora #%00000100 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_D3: ; SET 2,E lda REG_E ora #%00000100 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_D4: ; SET 2,H lda REG_H ora #%00000100 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_D5: ; SET 2,L lda REG_L ora #%00000100 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_D7: ; SET 2,A lda REG_A ora #%00000100 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_D8: ; SET 3,B lda REG_B ora #%00001000 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_D9: ; SET 3,C lda REG_C ora #%00001000 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_DA: ; SET 3,D lda REG_D ora #%00001000 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_DB: ; SET 3,E lda REG_E ora #%00001000 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_DC: ; SET 3,H lda REG_H ora #%00001000 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_DD: ; SET 3,L lda REG_L ora #%00001000 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_DF: ; SET 3,A lda REG_A ora #%00001000 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_E0: ; SET 4,B lda REG_B ora #%00010000 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_E1: ; SET 4,C lda REG_C ora #%00010000 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_E2: ; SET 4,D lda REG_D ora #%00010000 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_E3: ; SET 4,E lda REG_E ora #%00010000 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_E4: ; SET 4,H lda REG_H ora #%00010000 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_E5: ; SET 4,L lda REG_L ora #%00010000 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_E7: ; SET 4,A lda REG_A ora #%00010000 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_E8: ; SET 5,B lda REG_B ora #%00100000 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_E9: ; SET 5,C lda REG_C ora #%00100000 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_EA: ; SET 5,D lda REG_D ora #%00100000 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_EB: ; SET 5,E lda REG_E ora #%00100000 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_EC: ; SET 5,H lda REG_H ora #%00100000 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_ED: ; SET 5,L lda REG_L ora #%00100000 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_EF: ; SET 5,A lda REG_A ora #%00100000 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_F0: ; SET 6,B lda REG_B ora #%01000000 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_F1: ; SET 6,C lda REG_C ora #%01000000 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_F2: ; SET 6,D lda REG_D ora #%01000000 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_F3: ; SET 6,E lda REG_E ora #%01000000 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_F4: ; SET 6,H lda REG_H ora #%01000000 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_F5: ; SET 6,L lda REG_L ora #%01000000 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_F7: ; SET 6,A lda REG_A ora #%01000000 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_F8: ; SET 7,B lda REG_B ora #%10000000 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_F9: ; SET 7,C lda REG_C ora #%10000000 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_FA: ; SET 7,D lda REG_D ora #%10000000 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_FB: ; SET 7,E lda REG_E ora #%10000000 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_FC: ; SET 7,H lda REG_H ora #%10000000 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_FD: ; SET 7,L lda REG_L ora #%10000000 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_FF: ; SET 7,A lda REG_A ora #%10000000 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_C6: ; SET 0,(HL) jsr (VEC_fetch_via_HL) ora #%00000001 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_CE: ; SET 1,(HL) jsr (VEC_fetch_via_HL) ora #%00000010 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_D6: ; SET 2,(HL) jsr (VEC_fetch_via_HL) ora #%00000100 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_DE: ; SET 3,(HL) jsr (VEC_fetch_via_HL) ora #%00001000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_E6: ; SET 4,(HL) jsr (VEC_fetch_via_HL) ora #%00010000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_EE: ; SET 5,(HL) jsr (VEC_fetch_via_HL) ora #%00100000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_F6: ; SET 6,(HL) jsr (VEC_fetch_via_HL) ora #%01000000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_FE: ; SET 7,(HL) jsr (VEC_fetch_via_HL) ora #%10000000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_C6: ; SET 0,(IX+d) jsr (VEC_fetch_via_IX_d) ora #%00000001 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_CE: ; SET 1,(IX+d) jsr (VEC_fetch_via_IX_d) ora #%00000010 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_D6: ; SET 2,(IX+d) jsr (VEC_fetch_via_IX_d) ora #%00000100 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_DE: ; SET 3,(IX+d) jsr (VEC_fetch_via_IX_d) ora #%00001000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_E6: ; SET 4,(IX+d) jsr (VEC_fetch_via_IX_d) ora #%00010000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_EE: ; SET 5,(IX+d) jsr (VEC_fetch_via_IX_d) ora #%00100000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_F6: ; SET 6,(IX+d) jsr (VEC_fetch_via_IX_d) ora #%01000000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_FE: ; SET 7,(IX+d) jsr (VEC_fetch_via_IX_d) ora #%10000000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_C6: ; SET 0,(IY+d) jsr (VEC_fetch_via_IY_d) ora #%00000001 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_CE: ; SET 1,(IY+d) jsr (VEC_fetch_via_IY_d) ora #%00000010 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_D6: ; SET 2,(IY+d) jsr (VEC_fetch_via_IY_d) ora #%00000100 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_DE: ; SET 3,(IY+d) jsr (VEC_fetch_via_IY_d) ora #%00001000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_E6: ; SET 4,(IY+d) jsr (VEC_fetch_via_IY_d) ora #%00010000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_EE: ; SET 5,(IY+d) jsr (VEC_fetch_via_IY_d) ora #%00100000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_F6: ; SET 6,(IY+d) jsr (VEC_fetch_via_IY_d) ora #%01000000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_FE: ; SET 7,(IY+d) jsr (VEC_fetch_via_IY_d) ora #%10000000 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_80: ; RES 0,B lda REG_B and #%11111110 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_81: ; RES 0,C lda REG_C and #%11111110 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_82: ; RES 0,D lda REG_D and #%11111110 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_83: ; RES 0,E lda REG_E and #%11111110 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_84: ; RES 0,H lda REG_H and #%11111110 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_85: ; RES 0,L lda REG_L and #%11111110 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_87: ; RES 0,A lda REG_A and #%11111110 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_88: ; RES 1,B lda REG_B and #%11111101 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_89: ; RES 1,C lda REG_C and #%11111101 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_8A: ; RES 1,D lda REG_D and #%11111101 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_8B: ; RES 1,E lda REG_E and #%11111101 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_8C: ; RES 1,H lda REG_H and #%11111101 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_8D: ; RES 1,L lda REG_L and #%11111101 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_8F: ; RES 1,A lda REG_A and #%11111101 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_90: ; RES 2,B lda REG_B and #%11111011 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_91: ; RES 2,C lda REG_C and #%11111011 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_92: ; RES 2,D lda REG_D and #%11111011 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_93: ; RES 2,E lda REG_E and #%11111011 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_94: ; RES 2,H lda REG_H and #%11111011 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_95: ; RES 2,L lda REG_L and #%11111011 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_97: ; RES 2,A lda REG_A and #%11111011 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_98: ; RES 3,B lda REG_B and #%11110111 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_99: ; RES 3,C lda REG_C and #%11110111 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_9A: ; RES 3,D lda REG_D and #%11110111 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_9B: ; RES 3,E lda REG_E and #%11110111 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_9C: ; RES 3,H lda REG_H and #%11110111 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_9D: ; RES 3,L lda REG_L and #%11110111 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_9F: ; RES 3,A lda REG_A and #%11110111 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_A0: ; RES 4,B lda REG_B and #%11101111 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_A1: ; RES 4,C lda REG_C and #%11101111 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_A2: ; RES 4,D lda REG_D and #%11101111 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_A3: ; RES 4,E lda REG_E and #%11101111 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_A4: ; RES 4,H lda REG_H and #%11101111 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_A5: ; RES 4,L lda REG_L and #%11101111 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_A7: ; RES 4,A lda REG_A and #%11101111 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_A8: ; RES 5,B lda REG_B and #%11011111 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_A9: ; RES 5,C lda REG_C and #%11011111 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_AA: ; RES 5,D lda REG_D and #%11011111 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_AB: ; RES 5,E lda REG_E and #%11011111 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_AC: ; RES 5,H lda REG_H and #%11011111 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_AD: ; RES 5,L lda REG_L and #%11011111 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_AF: ; RES 5,A lda REG_A and #%11011111 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_B0: ; RES 6,B lda REG_B and #%10111111 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_B1: ; RES 6,C lda REG_C and #%10111111 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_B2: ; RES 6,D lda REG_D and #%10111111 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_B3: ; RES 6,E lda REG_E and #%10111111 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_B4: ; RES 6,H lda REG_H and #%10111111 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_B5: ; RES 6,L lda REG_L and #%10111111 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_B7: ; RES 6,A lda REG_A and #%10111111 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_B8: ; RES 7,B lda REG_B and #%01111111 sta REG_B - rts + jmp ZVM_next Z80_instr_CB_B9: ; RES 7,C lda REG_C and #%01111111 sta REG_C - rts + jmp ZVM_next Z80_instr_CB_BA: ; RES 7,D lda REG_D and #%01111111 sta REG_D - rts + jmp ZVM_next Z80_instr_CB_BB: ; RES 7,E lda REG_E and #%01111111 sta REG_E - rts + jmp ZVM_next Z80_instr_CB_BC: ; RES 7,H lda REG_H and #%01111111 sta REG_H - rts + jmp ZVM_next Z80_instr_CB_BD: ; RES 7,L lda REG_L and #%01111111 sta REG_L - rts + jmp ZVM_next Z80_instr_CB_BF: ; RES 7,A lda REG_A and #%01111111 sta REG_A - rts + jmp ZVM_next Z80_instr_CB_86: ; RES 0,(HL) jsr (VEC_fetch_via_HL) and #%11111110 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_8E: ; RES 1,(HL) jsr (VEC_fetch_via_HL) and #%11111101 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_96: ; RES 2,(HL) jsr (VEC_fetch_via_HL) and #%11111011 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_9E: ; RES 3,(HL) jsr (VEC_fetch_via_HL) and #%11110111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_A6: ; RES 4,(HL) jsr (VEC_fetch_via_HL) and #%11101111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_AE: ; RES 5,(HL) jsr (VEC_fetch_via_HL) and #%11011111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_B6: ; RES 6,(HL) jsr (VEC_fetch_via_HL) and #%10111111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_CB_BE: ; RES 7,(HL) jsr (VEC_fetch_via_HL) and #%01111111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_86: ; RES 0,(IX+d) jsr (VEC_fetch_via_IX_d) and #%11111110 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_8E: ; RES 1,(IX+d) jsr (VEC_fetch_via_IX_d) and #%11111101 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_96: ; RES 2,(IX+d) jsr (VEC_fetch_via_IX_d) and #%11111011 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_9E: ; RES 3,(IX+d) jsr (VEC_fetch_via_IX_d) and #%11110111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_A6: ; RES 4,(IX+d) jsr (VEC_fetch_via_IX_d) and #%11101111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_AE: ; RES 5,(IX+d) jsr (VEC_fetch_via_IX_d) and #%11011111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_B6: ; RES 6,(IX+d) jsr (VEC_fetch_via_IX_d) and #%10111111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_DDCB_BE: ; RES 7,(IX+d) jsr (VEC_fetch_via_IX_d) and #%01111111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_86: ; RES 0,(IY+d) jsr (VEC_fetch_via_IY_d) and #%11111110 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_8E: ; RES 1,(IY+d) jsr (VEC_fetch_via_IY_d) and #%11111101 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_96: ; RES 2,(IY+d) jsr (VEC_fetch_via_IY_d) and #%11111011 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_9E: ; RES 3,(IY+d) jsr (VEC_fetch_via_IY_d) and #%11110111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_A6: ; RES 4,(IY+d) jsr (VEC_fetch_via_IY_d) and #%11101111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_AE: ; RES 5,(IY+d) jsr (VEC_fetch_via_IY_d) and #%11011111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_B6: ; RES 6,(IY+d) jsr (VEC_fetch_via_IY_d) and #%10111111 - jmp ZVM_store_back + jmp ZVM_store_next Z80_instr_FDCB_BE: ; RES 7,(IY+d) jsr (VEC_fetch_via_IY_d) and #%01111111 - jmp ZVM_store_back + jmp ZVM_store_next diff --git a/src/zvm_m65/z80_instr_exchange.s b/src/zvm_m65/z80_instr_exchange.s index 89ab60e3..ac3b149f 100644 --- a/src/zvm_m65/z80_instr_exchange.s +++ b/src/zvm_m65/z80_instr_exchange.s @@ -16,7 +16,7 @@ Z80_instr_EB: ; EX DE,HL sty REG_E stx REG_L - rts + jmp ZVM_next Z80_instr_08: ; EX AF,AF'' @@ -30,7 +30,7 @@ Z80_instr_08: ; EX AF,AF'' sty REG_F stx REG_F_SH - rts + jmp ZVM_next Z80_instr_D9: ; EXX @@ -64,4 +64,4 @@ Z80_instr_D9: ; EXX sty REG_L stx REG_L_SH - rts + jmp ZVM_next diff --git a/src/zvm_m65/z80_instr_general.s b/src/zvm_m65/z80_instr_general.s index efe1aef0..c9d90897 100644 --- a/src/zvm_m65/z80_instr_general.s +++ b/src/zvm_m65/z80_instr_general.s @@ -29,7 +29,7 @@ Z80_instr_ED_5E: ; IM 2 ; Real NOP Z80_instr_00: ; NOP - rts + jmp ZVM_next Z80_instr_F3: ; DI @@ -43,4 +43,4 @@ Z80_instr_FB: ; EI lda #Z80_PF sta REG_IFF1 sta REG_IFF2 - rts + jmp ZVM_next diff --git a/src/zvm_m65/z80_instr_jump.s b/src/zvm_m65/z80_instr_jump.s index fb4aa4a8..b4a8766e 100644 --- a/src/zvm_m65/z80_instr_jump.s +++ b/src/zvm_m65/z80_instr_jump.s @@ -10,60 +10,60 @@ Z80_instr_C3: ; JP nn sta REG_PC+0 jsr (VEC_fetch_value) sta REG_PC+1 - rts + jmp ZVM_next Z80_instr_C2: ; JP NZ,nn bbr6 REG_F,Z80_instr_C3 inw REG_PC inw REG_PC - rts + jmp ZVM_next Z80_instr_CA: ; JP Z,nn bbs6 REG_F,Z80_instr_C3 inw REG_PC inw REG_PC - rts + jmp ZVM_next Z80_instr_D2: ; JP NC,nn bbr0 REG_F,Z80_instr_C3 inw REG_PC inw REG_PC - rts + jmp ZVM_next Z80_instr_DA: ; JP C,nn bbs0 REG_F,Z80_instr_C3 inw REG_PC inw REG_PC - rts + jmp ZVM_next Z80_instr_E2: ; JP PO,nn bbr2 REG_F,Z80_instr_C3 inw REG_PC inw REG_PC - rts + jmp ZVM_next Z80_instr_EA: ; JP PE,nn bbs2 REG_F,Z80_instr_C3 inw REG_PC inw REG_PC - rts + jmp ZVM_next Z80_instr_F2: ; JP P,nn bbr7 REG_F,Z80_instr_C3 inw REG_PC inw REG_PC - rts + jmp ZVM_next Z80_instr_FA: ; JP M,nn bbs7 REG_F,Z80_instr_C3 inw REG_PC inw REG_PC - rts + jmp ZVM_next diff --git a/src/zvm_m65/z80_instr_load_8bit.s b/src/zvm_m65/z80_instr_load_8bit.s index 67945b99..a6a46e13 100644 --- a/src/zvm_m65/z80_instr_load_8bit.s +++ b/src/zvm_m65/z80_instr_load_8bit.s @@ -12,175 +12,175 @@ Z80_instr_41: ; LD B,C lda REG_C sta REG_B - rts + jmp ZVM_next Z80_instr_42: ; LD B,D lda REG_D sta REG_B - rts + jmp ZVM_next Z80_instr_43: ; LD B,E lda REG_E sta REG_B - rts + jmp ZVM_next Z80_instr_44: ; LD B,H lda REG_H sta REG_B - rts + jmp ZVM_next Z80_instr_45: ; LD B,L lda REG_L sta REG_B - rts + jmp ZVM_next Z80_instr_47: ; LD B,A lda REG_A sta REG_B - rts + jmp ZVM_next Z80_instr_48: ; LD C,B lda REG_B sta REG_C - rts + jmp ZVM_next Z80_instr_4A: ; LD C,D lda REG_D sta REG_C - rts + jmp ZVM_next Z80_instr_4B: ; LD C,E lda REG_E sta REG_C - rts + jmp ZVM_next Z80_instr_4C: ; LD C,H lda REG_H sta REG_C - rts + jmp ZVM_next Z80_instr_4D: ; LD C,L lda REG_L sta REG_C - rts + jmp ZVM_next Z80_instr_4F: ; LD C,A lda REG_A sta REG_C - rts + jmp ZVM_next Z80_instr_50: ; LD D,B lda REG_B sta REG_D - rts + jmp ZVM_next Z80_instr_51: ; LD D,C lda REG_C sta REG_D - rts + jmp ZVM_next Z80_instr_53: ; LD D,E lda REG_E sta REG_D - rts + jmp ZVM_next Z80_instr_54: ; LD D,H lda REG_H sta REG_D - rts + jmp ZVM_next Z80_instr_55: ; LD D,L lda REG_L sta REG_D - rts + jmp ZVM_next Z80_instr_57: ; LD D,A lda REG_A sta REG_D - rts + jmp ZVM_next Z80_instr_58: ; LD E,B lda REG_B sta REG_E - rts + jmp ZVM_next Z80_instr_59: ; LD E,C lda REG_C sta REG_E - rts + jmp ZVM_next Z80_instr_5A: ; LD E,D lda REG_D sta REG_E - rts + jmp ZVM_next Z80_instr_5C: ; LD E,H lda REG_H sta REG_E - rts + jmp ZVM_next Z80_instr_5D: ; LD E,L lda REG_L sta REG_E - rts + jmp ZVM_next Z80_instr_5F: ; LD E,A lda REG_A sta REG_E - rts + jmp ZVM_next Z80_instr_60: ; LD H,B lda REG_B sta REG_H - rts + jmp ZVM_next Z80_instr_61: ; LD H,C lda REG_C sta REG_H - rts + jmp ZVM_next Z80_instr_62: ; LD H,D lda REG_D sta REG_H - rts + jmp ZVM_next Z80_instr_63: ; LD H,E lda REG_E sta REG_H - rts + jmp ZVM_next Z80_instr_65: ; LD H,L lda REG_L sta REG_H - rts + jmp ZVM_next Z80_instr_67: ; LD H,A @@ -192,73 +192,73 @@ Z80_instr_68: ; LD L,B lda REG_B sta REG_L - rts + jmp ZVM_next Z80_instr_69: ; LD L,C lda REG_C sta REG_L - rts + jmp ZVM_next Z80_instr_6A: ; LD L,D lda REG_D sta REG_L - rts + jmp ZVM_next Z80_instr_6B: ; LD L,E lda REG_E sta REG_L - rts + jmp ZVM_next Z80_instr_6C: ; LD L,H lda REG_H sta REG_L - rts + jmp ZVM_next Z80_instr_6F: ; LD L,A lda REG_A sta REG_L - rts + jmp ZVM_next Z80_instr_78: ; LD A,B lda REG_B sta REG_A - rts + jmp ZVM_next Z80_instr_79: ; LD A,C lda REG_C sta REG_A - rts + jmp ZVM_next Z80_instr_7A: ; LD A,D lda REG_D sta REG_A - rts + jmp ZVM_next Z80_instr_7B: ; LD A,E lda REG_E sta REG_A - rts + jmp ZVM_next Z80_instr_7C: ; LD A,H lda REG_H sta REG_A - rts + jmp ZVM_next Z80_instr_7D: ; LD A,L lda REG_L sta REG_A - rts + jmp ZVM_next ; ; load register with immediate value @@ -268,43 +268,43 @@ Z80_instr_06: ; LD B,n jsr (VEC_fetch_value) sta REG_B - rts + jmp ZVM_next Z80_instr_0E: ; LD C,n jsr (VEC_fetch_value) sta REG_C - rts + jmp ZVM_next Z80_instr_16: ; LD D,n jsr (VEC_fetch_value) sta REG_D - rts + jmp ZVM_next Z80_instr_1E: ; LD E,n jsr (VEC_fetch_value) sta REG_E - rts + jmp ZVM_next Z80_instr_26: ; LD H,n jsr (VEC_fetch_value) sta REG_H - rts + jmp ZVM_next Z80_instr_2E: ; LD L,n jsr (VEC_fetch_value) sta REG_L - rts + jmp ZVM_next Z80_instr_3E: ; LD A,n jsr (VEC_fetch_value) sta REG_A - rts + jmp ZVM_next ; ; load register with memory content (via HL) @@ -314,43 +314,43 @@ Z80_instr_46: ; LD B,(HL) jsr (VEC_fetch_via_HL) sta REG_B - rts + jmp ZVM_next Z80_instr_4E: ; LD C,(HL) jsr (VEC_fetch_via_HL) sta REG_C - rts + jmp ZVM_next Z80_instr_56: ; LD D,(HL) jsr (VEC_fetch_via_HL) sta REG_D - rts + jmp ZVM_next Z80_instr_5E: ; LD E,(HL) jsr (VEC_fetch_via_HL) sta REG_E - rts + jmp ZVM_next Z80_instr_66: ; LD H,(HL) jsr (VEC_fetch_via_HL) sta REG_H - rts + jmp ZVM_next Z80_instr_6E: ; LD L,(HL) jsr (VEC_fetch_via_HL) sta REG_L - rts + jmp ZVM_next Z80_instr_7E: ; LD A,(HL) jsr (VEC_fetch_via_HL) sta REG_A - rts + jmp ZVM_next ; XXX put here LD r,(IX+d) family ; XXX put here LD r,(IY+d) family diff --git a/src/zvm_m65/z80_instr_math_16bit.s b/src/zvm_m65/z80_instr_math_16bit.s index cbbcef28..3cef4337 100644 --- a/src/zvm_m65/z80_instr_math_16bit.s +++ b/src/zvm_m65/z80_instr_math_16bit.s @@ -7,59 +7,59 @@ Z80_instr_03: ; INC BC inw REG_C - rts + jmp ZVM_next Z80_instr_13: ; INC DE inw REG_E - rts + jmp ZVM_next Z80_instr_23: ; INC HL inw REG_L - rts + jmp ZVM_next Z80_instr_33: ; INC SP inw REG_SP - rts + jmp ZVM_next Z80_instr_DD_23: ; INC IX inw REG_IX - rts + jmp ZVM_next Z80_instr_FD_23: ; INC IY inw REG_IY - rts + jmp ZVM_next Z80_instr_0B: ; DEC BC dew REG_C - rts + jmp ZVM_next Z80_instr_1B: ; DEC DE dew REG_E - rts + jmp ZVM_next Z80_instr_2B: ; DEC HL dew REG_L - rts + jmp ZVM_next Z80_instr_3B: ; DEC SP dew REG_SP - rts + jmp ZVM_next Z80_instr_DD_2B: ; DEC IX dew REG_IX - rts + jmp ZVM_next Z80_instr_FD_2B: ; DEC IY dew REG_IY - rts + jmp ZVM_next diff --git a/src/zvm_m65/z80_instr_math_8bit.s b/src/zvm_m65/z80_instr_math_8bit.s index 0be65960..87849057 100644 --- a/src/zvm_m65/z80_instr_math_8bit.s +++ b/src/zvm_m65/z80_instr_math_8bit.s @@ -60,14 +60,14 @@ Z80_common_INC: and #(0xFF - Z80_SF - Z80_ZF - Z80_HF - Z80_VF - Z80_NF) ora z80_ftable_INC, x sta REG_F - rts + jmp ZVM_next Z80_instr_34: ; INC (HL) jsr (VEC_fetch_via_HL) tax inc - jsr ZVM_store_back + sta [PTR_DATA],z bra Z80_common_INC Z80_instr_DD_34: ; INC (IX+d) @@ -75,7 +75,7 @@ Z80_instr_DD_34: ; INC (IX+d) jsr (VEC_fetch_via_IX_d) tax inc - jsr ZVM_store_back + sta [PTR_DATA],z bra Z80_common_INC Z80_instr_FD_34: ; INC (IY+d) @@ -83,7 +83,7 @@ Z80_instr_FD_34: ; INC (IY+d) jsr (VEC_fetch_via_IY_d) tax inc - jsr ZVM_store_back + sta [PTR_DATA],z bra Z80_common_INC Z80_instr_05: ; DEC B @@ -135,14 +135,14 @@ Z80_common_DEC: and #(0xFF - Z80_SF - Z80_ZF - Z80_HF - Z80_VF - Z80_NF) ora z80_ftable_DEC, x sta REG_F - rts + jmp ZVM_next Z80_instr_35: ; DEC (HL) jsr (VEC_fetch_via_HL) tax dec - jsr ZVM_store_back + sta [PTR_DATA],z bra Z80_common_DEC Z80_instr_DD_35: ; DEC (IX+d) @@ -150,7 +150,7 @@ Z80_instr_DD_35: ; DEC (IX+d) jsr (VEC_fetch_via_IX_d) tax dec - jsr ZVM_store_back + sta [PTR_DATA],z bra Z80_common_DEC Z80_instr_FD_35: ; DEC (IY+d) @@ -158,5 +158,5 @@ Z80_instr_FD_35: ; DEC (IY+d) jsr (VEC_fetch_via_IY_d) tax dec - jsr ZVM_store_back + sta [PTR_DATA],z bra Z80_common_DEC diff --git a/src/zvm_m65/zvm_banking.s b/src/zvm_m65/zvm_banking.s index 009aef8a..9b365191 100644 --- a/src/zvm_m65/zvm_banking.s +++ b/src/zvm_m65/zvm_banking.s @@ -146,24 +146,66 @@ ZVM_fetch_value_bank_0: ZVM_fetch_value_bank_1: ZVM_fetch_stack_bank_0: ZVM_fetch_stack_bank_1: -ZVM_store_stack_bank_0: -ZVM_store_stack_bank_1: ZVM_fetch_via_HL_bank_0: ZVM_fetch_via_HL_bank_1: -ZVM_store_via_HL_bank_0: -ZVM_store_via_HL_bank_1: ZVM_fetch_via_IX_d_bank_0: ZVM_fetch_via_IX_d_bank_1: ZVM_fetch_via_IY_d_bank_0: ZVM_fetch_via_IY_d_bank_1: -ZVM_store_via_IX_d_bank_0: -ZVM_store_via_IX_d_bank_1: -ZVM_store_via_IY_d_bank_0: -ZVM_store_via_IY_d_bank_1: ZVM_fetch_via_nn_bank_0: ZVM_fetch_via_nn_bank_1: -ZVM_store_via_nn_bank_0: -ZVM_store_via_nn_bank_1: -ZVM_store_back: - ; XXX implement these + ; XXX + rts + + +ZVM_store_stack_bank_0: + + ; XXX + jmp ZVM_next + +ZVM_store_stack_bank_1: + + ; XXX + jmp ZVM_next + +ZVM_store_via_HL_bank_0: + + ; XXX + jmp ZVM_next + +ZVM_store_via_HL_bank_1: + + ; XXX + jmp ZVM_next + +ZVM_store_via_IX_d_bank_0: + + ; XXX + jmp ZVM_next + +ZVM_store_via_IX_d_bank_1: + + ; XXX + jmp ZVM_next + +ZVM_store_via_IY_d_bank_0: + + ; XXX + jmp ZVM_next + +ZVM_store_via_IY_d_bank_1: + + ; XXX + jmp ZVM_next + +ZVM_store_via_nn_bank_0: + + ; XXX + jmp ZVM_next + +ZVM_store_via_nn_bank_1: + + ; XXX + jmp ZVM_next + diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s index 1d267c9e..c9e50973 100644 --- a/src/zvm_m65/zvm_core.s +++ b/src/zvm_m65/zvm_core.s @@ -7,10 +7,14 @@ ZVM_entry: jsr ZVM_init ; XXX fetch BDOS and Command Processor - jmp ZVM_run + jmp ZVM_next ZVM_init: + ; .Z is required to be 0 all the time + + ldz #$00 + ; Reset all the registers lda #$00 @@ -24,9 +28,14 @@ ZVM_init: ; XXX what is the initial SP value? ; XXX clean memory - jmp ZVM_set_bank_0 - -ZVM_run: + jmp ZVM_set_bank_1 + + +ZVM_store_next: + + sta [PTR_DATA],z + +ZVM_next: ; fetch and execute next opcode ; CPU main loop @@ -85,10 +94,6 @@ ZVM_run: - - - -