From 31b3bc38c932b36bee82a03d60174cb9c872cc51 Mon Sep 17 00:00:00 2001 From: FeralChild64 Date: Tue, 26 May 2020 22:21:23 +0200 Subject: [PATCH] handle all 4 SIDs on Mega65, tape turbo SFX should play on both left and right channels --- CONFIG.md | 4 ++-- c64/,,config_mega65.s | 2 +- c64/aliases/,aliases_config.s | 4 ++++ c64/aliases/,aliases_hardware.s | 9 +++++++++ c64/kernal/init/fda3.ioinit.s | 17 +++++++++++++++-- c64/kernal/tape/tape_common_autodetect.s | 5 +++++ c64/kernal/tape/tape_common_clean_sid.s | 15 +++++++++++++++ c64/kernal/tape/tape_turbo_get_bit.s | 10 ++++++++++ 8 files changed, 61 insertions(+), 5 deletions(-) diff --git a/CONFIG.md b/CONFIG.md index 48a6e652..35ae74b1 100644 --- a/CONFIG.md +++ b/CONFIG.md @@ -187,7 +187,7 @@ The SID support in the ROM is very limited - it only disables the sound during s ### `CONFIG_SID_2ND` and `CONFIG_SID_3RD` -Each of them add support for one additional SID - addresses should be given in `CONFIG_SID_2ND_ADDRESS` and `CONFIG_SID_3RD_ADDRESS`, respectively. +Each of them add support for one additional SID - addresses should be given in `CONFIG_SID_2ND_ADDRESS` and `CONFIG_SID_3RD_ADDRESS`, respectively. Do not use when `CONFIG_MB_MEGA_65` is selected - the motherboard support code already knows the SID locations. Each of these options needs 3 bytes in KERNAL segment. @@ -195,7 +195,7 @@ Each of these options needs 3 bytes in KERNAL segment. Cause the system to support SIDs in `$D4xx` and `$D5xx` ranges, respectively. -Each of them needs a couple of bytes in KERNAL segment - but they can share some code, and `$D4xx` range support replaces the standard `$D400` address handling, so exact amount depends on the exact configuration. +Each of them needs a couple of bytes in KERNAL segment - but they can share some code, and `$D4xx` range support replaces the standard `$D400` address handling, so exact amount depends on the exact configuration. Do not use when `CONFIG_MB_MEGA_65` is selected - the motherboard support code already knows the SID locations. ## Keyboard diff --git a/c64/,,config_mega65.s b/c64/,,config_mega65.s index 6bd9ee5c..d21b369f 100644 --- a/c64/,,config_mega65.s +++ b/c64/,,config_mega65.s @@ -58,7 +58,7 @@ // Multiple SID support -#define CONFIG_SID_2ND +// #define CONFIG_SID_2ND .const CONFIG_SID_2ND_ADDRESS = $D440 // #define CONFIG_SID_3RD diff --git a/c64/aliases/,aliases_config.s b/c64/aliases/,aliases_config.s index 57fb1c9f..752a452e 100644 --- a/c64/aliases/,aliases_config.s +++ b/c64/aliases/,aliases_config.s @@ -42,6 +42,10 @@ #if !CONFIG_PLATFORM_COMMODORE_64 && CONFIG_BRAND_ULTIMATE_64 && .error "CONFIG_BRAND_ULTIMATE_64 can only be used with CONFIG_PLATFORM_COMMODORE_64" #endif + +#if CONFIG_MB_MEGA_65 && (CONFIG_SID_2ND || CONFIG_SID_3RD || CONFIG_SID_D4XX || CONFIG_SID_D5XX) + .error "CONFIG_MB_MEGA_65 cannot be used with CONFIG_SID_*" +#endif } diff --git a/c64/aliases/,aliases_hardware.s b/c64/aliases/,aliases_hardware.s index e7a7a51c..f03458c9 100644 --- a/c64/aliases/,aliases_hardware.s +++ b/c64/aliases/,aliases_hardware.s @@ -83,6 +83,15 @@ .label __SID_BASE = $D400 // base address of the chip +#if CONFIG_MB_MEGA_65 + + .label __SID_R1_OFFSET = $00 // right SID 1, $D400 + .label __SID_R2_OFFSET = $20 // right SID 2, $D420 + .label __SID_L1_OFFSET = $40 // left SID 1, $D440 + .label __SID_L2_OFFSET = $60 // left SID 2, $D460 + +#endif + .label SID_FRELO1 = $D400 .label SID_FREHI1 = $D401 .label SID_PWLO1 = $D402 diff --git a/c64/kernal/init/fda3.ioinit.s b/c64/kernal/init/fda3.ioinit.s index 35d07223..b5cfc31d 100644 --- a/c64/kernal/init/fda3.ioinit.s +++ b/c64/kernal/init/fda3.ioinit.s @@ -59,10 +59,12 @@ IOINIT: // Now silence the SID chip(s), depending on the configuration - we want them silent ASAP // - // First the standard chip (skip if it is covered by whole $D4XX range) - lda #$00 +#if !CONFIG_MB_MEGA65 + + // First the standard chip (skip if it is covered by whole $D4XX range) + #if !CONFIG_SID_D4XX sta SID_SIGVOL #endif // !CONFIG_SID_D4XX @@ -100,6 +102,17 @@ IOINIT: #endif // CONFIG_SID_D4XX || CONFIG_SID_D5XX +#else + + // Mega65 specific handling - it contains 4 SIDs + + sta SID_SIGVOL + __SID_R1_OFFSET + sta SID_SIGVOL + __SID_R2_OFFSET + sta SID_SIGVOL + __SID_L1_OFFSET + sta SID_SIGVOL + __SID_L2_OFFSET + +#endif // CONFIG_MB_MEGA65 + // // Now continue the CIAs initialization // diff --git a/c64/kernal/tape/tape_common_autodetect.s b/c64/kernal/tape/tape_common_autodetect.s index 5ea9aebe..07f60842 100644 --- a/c64/kernal/tape/tape_common_autodetect.s +++ b/c64/kernal/tape/tape_common_autodetect.s @@ -17,7 +17,12 @@ tape_common_autodetect: lda #$0B sta VIC_EXTCOL lda #$00 +#if CONFIG_MB_MEGA65 + sta SID_SIGVOL + __SID_R1_OFFSET + sta SID_SIGVOL + __SID_L1_OFFSET +#else sta SID_SIGVOL +#endif // FALLTROUGH diff --git a/c64/kernal/tape/tape_common_clean_sid.s b/c64/kernal/tape/tape_common_clean_sid.s index a320faef..f91b8c6e 100644 --- a/c64/kernal/tape/tape_common_clean_sid.s +++ b/c64/kernal/tape/tape_common_clean_sid.s @@ -15,7 +15,22 @@ tape_clean_sid: lda #$00 ldy #$1C !: + +#if CONFIG_MB_MEGA65 + + // It should be safer than cleaning whole $D400-D47C range + + sta __SID_BASE + __SID_R1_OFFSET, y + sta __SID_BASE + __SID_R2_OFFSET, y + sta __SID_BASE + __SID_L1_OFFSET, y + sta __SID_BASE + __SID_L2_OFFSET, y + +#else + sta __SID_BASE, y + +#endif + dey bpl !- diff --git a/c64/kernal/tape/tape_turbo_get_bit.s b/c64/kernal/tape/tape_turbo_get_bit.s index a903a4d5..f2718cff 100644 --- a/c64/kernal/tape/tape_turbo_get_bit.s +++ b/c64/kernal/tape/tape_turbo_get_bit.s @@ -23,7 +23,12 @@ tape_turbo_get_bit: sta __turbo_half_S // store half of the last measurement result for short pulse lda #$01 +#if CONFIG_MB_MEGA65 + sta SID_SIGVOL + __SID_R1_OFFSET + sta SID_SIGVOL + __SID_L1_OFFSET +#else sta SID_SIGVOL +#endif lda #$06 sta VIC_EXTCOL sec @@ -34,7 +39,12 @@ tape_turbo_get_bit: sta __turbo_half_L // store half of the last measurement result for long pulse lda #$00 +#if CONFIG_MB_MEGA65 + sta SID_SIGVOL + __SID_R1_OFFSET + sta SID_SIGVOL + __SID_L1_OFFSET +#else sta SID_SIGVOL +#endif sta VIC_EXTCOL clc rts