diff --git a/CONFIG.md b/CONFIG.md index 06cc3736..0572f73d 100644 --- a/CONFIG.md +++ b/CONFIG.md @@ -105,9 +105,9 @@ Needs over 1000 bytes in KERNAL segment. If unsure - enable. ### `CONFIG_IEC_JIFFYDOS` -Adds support for JiffyDOS pprotocol to the IEC bus (note, that it currentlyy lacks the optimized LOAD loop, so it will be slower than original JiffyDOS enabled Kernal ROMs). +Adds support for JiffyDOS fast protocol to the IEC bus. -Needs over 320 bytes in KERNAL segment. If unsure - enable. +Needs about 420 bytes in KERNAL segment. If unsure - enable. ### `CONFIG_TAPE_TURBO` diff --git a/STATUS.md b/STATUS.md index 99605adb..fdda84ef 100644 --- a/STATUS.md +++ b/STATUS.md @@ -8,11 +8,12 @@ Here are the features of the Open ROMs not found in the original ROMs from the 8 * pre-defined function keys * uses RAM under ROM and I/O: 61438 bytes free * cold/warm start silences multiple SID chips - all $D4xx and $D5xx addresses, configured addresses -* wark start due to BRK prints out the instruction address +* warm start due to BRK prints out the instruction address * extended `LOAD` command * start/end addresses are displayed, in the Final cartridge style * command with just the file name tries to use the last device if it's number seems sane; otherwise uses 8 * secondary address over 255 is considered a start address +* JiffyDOS protocol support * turbo tape load support (as device 7 or using `←L`) * DOS wedge (direct mode only) - `@`, `@`, `@$`, `@$`, `@` diff --git a/bin/basic_generic.rom b/bin/basic_generic.rom index a20878cb..ebdb04d8 100644 Binary files a/bin/basic_generic.rom and b/bin/basic_generic.rom differ diff --git a/bin/basic_mega65.rom b/bin/basic_mega65.rom index e988783a..fdf8a5e2 100644 Binary files a/bin/basic_mega65.rom and b/bin/basic_mega65.rom differ diff --git a/bin/basic_testing.rom b/bin/basic_testing.rom index 4d05189a..fee95438 100644 Binary files a/bin/basic_testing.rom and b/bin/basic_testing.rom differ diff --git a/bin/basic_ultimate64.rom b/bin/basic_ultimate64.rom index 26d834de..6f12ef0a 100644 Binary files a/bin/basic_ultimate64.rom and b/bin/basic_ultimate64.rom differ diff --git a/bin/kernal_generic.rom b/bin/kernal_generic.rom index dbfb5b2d..c5e7be09 100644 Binary files a/bin/kernal_generic.rom and b/bin/kernal_generic.rom differ diff --git a/bin/kernal_mega65.rom b/bin/kernal_mega65.rom index fa7d782a..429d1c1c 100644 Binary files a/bin/kernal_mega65.rom and b/bin/kernal_mega65.rom differ diff --git a/bin/kernal_testing.rom b/bin/kernal_testing.rom index 2ad0274c..316e8159 100644 Binary files a/bin/kernal_testing.rom and b/bin/kernal_testing.rom differ diff --git a/bin/kernal_ultimate64.rom b/bin/kernal_ultimate64.rom index 29bd3da4..97670f04 100644 Binary files a/bin/kernal_ultimate64.rom and b/bin/kernal_ultimate64.rom differ diff --git a/c64/kernal/iec/load_iec.s b/c64/kernal/iec/load_iec.s index 43a5419a..6379aefd 100644 --- a/c64/kernal/iec/load_iec.s +++ b/c64/kernal/iec/load_iec.s @@ -87,7 +87,23 @@ load_iec: // Display start address jsr lvs_display_loading_verifying -iec_load_loop: +#if CONFIG_IEC_JIFFYDOS + + // If feasible, use JiffyDOS optimized LOAD loop + + lda VERCKK + bne load_iec_loop // branch if VERIFY + + lda IECPROTO + cmp #$01 + bne load_iec_loop // branch if not JiffyDOS + + jmp load_jiffydos + +#endif + +load_iec_loop: + // We are now ready to receive bytes #if CONFIG_IEC_JIFFYDOS jsr iec_rx_dispatch @@ -118,7 +134,11 @@ iec_load_loop: // Check for EOI - if so, this was the last byte lda IOSTATUS and #K_STS_EOI - beq iec_load_loop + beq load_iec_loop + + // FALLTROUGH + +load_iec_loop_end: // Display end address jsr lvs_display_done diff --git a/c64/kernal/iec_fast/load_jiffydos.s b/c64/kernal/iec_fast/load_jiffydos.s new file mode 100644 index 00000000..e9b858cd --- /dev/null +++ b/c64/kernal/iec_fast/load_jiffydos.s @@ -0,0 +1,117 @@ + +// +// JiffyDOS protocol support for IEC - optimized load loop +// + + +#if CONFIG_IEC_JIFFYDOS + + + // XXX add RUN/STOP support + +load_jiffydos: + + // Timing is critical, do not allow interrupts + sei + + // Store previous sprite status in temporary variable + jsr jiffydos_prepare + sta TBTCNT + + // XXX For the first iteration load the whole sector minus 2 bytes + // XXX (as they are used to store the start address) + // XXX ldy #$FB + ldy #$00 + + // FALLTROUGH + +load_jiffydos_loop: + + // Wait until device is ready to send + jsr iec_wait_for_clk_release + + // Prepare 'start sending' message + lda CIA2_PRA + and #$FF - BIT_CIA2_PRA_DAT_OUT // release + tax + + // Wait for appropriate moment + jsr jiffydos_wait_line // XXX try to inline this, maybe one raster is enough? + + // Ask device to start sending bits + stx CIA2_PRA // cycles: 4 + + // Prepare 'data pull' byte, cycles: 3 + 2 + 2 = 7 + lda C3PO + ora #BIT_CIA2_PRA_DAT_OUT // pull + tax + + // Delay, JiffyDOS needs some time, 4 cycles + nop + nop + + // Get bits, cycles: 4 + 2 + 2 = 8 + lda CIA2_PRA // bits 0 and 1 on CLK/DATA + lsr + lsr + + // Wait for the drive, cycles: 2 + nop + + // Get bits, cycles: 4 + 2 + 2 = 8 + ora CIA2_PRA // bits 2 and 3 on CLK/DATA + lsr + lsr + + // Get bits, cycles: 3 + 4 + 2 + 2 = 11 + eor C3PO + eor CIA2_PRA // bits 4 and 5 on CLK/DATA + lsr + lsr + + // Get bits, cycles: 3 + 4 = 7 + eor C3PO + eor CIA2_PRA // bits 6 and 7 on CLK/DATA + + // Store retrieved byte, cycles: 6 + sta (EAL),y + + // Retrieve status bits, cycles: 4 + bit CIA2_PRA + + // Pull DATA at the end, cycles: 4 + stx CIA2_PRA + + // If CLK line not active - this was the last byte + bvs load_jiffydos_end + + // Advance pointer to data XXX use INY instead, advance once per sector only + jsr lvs_advance_EAL + + jmp load_jiffydos_loop + +load_jiffydos_end: + + // Save last byyte + tax + + // Indicate that no byte waits in output buffer + lda #$00 + sta C3PO + + // Restore proper IECPROTO value + lda #$01 + sta IECPROTO + + // Re-enable sprites + lda TBTCNT + sta VIC_SPENA + + // Store last byte as unoptimized LOAD would + stx TBTCNT + + // End of load loop + jmp load_iec_loop_end + + +#endif // CONFIG_IEC_JIFFYDOS