From 64dcf7193b6b5e16e808942bd20ebdb59358c8fc Mon Sep 17 00:00:00 2001 From: FeralChild64 Date: Mon, 21 Dec 2020 23:28:12 +0100 Subject: [PATCH] turned more repeating code into macros --- src/zvm_m65/z80_instr_load_16bit.s | 15 ++ src/zvm_m65/z80_instr_load_8bit.s | 307 +++++------------------------ src/zvm_m65/zvm_core.s | 8 +- 3 files changed, 69 insertions(+), 261 deletions(-) diff --git a/src/zvm_m65/z80_instr_load_16bit.s b/src/zvm_m65/z80_instr_load_16bit.s index 265589fc..fa41e3e8 100644 --- a/src/zvm_m65/z80_instr_load_16bit.s +++ b/src/zvm_m65/z80_instr_load_16bit.s @@ -4,6 +4,21 @@ ; +!macro Z80_LD_REGnn_nn .REGnn { + jsr (VEC_fetch_value) + sta .REGnn+0 + jsr (VEC_fetch_value) + sta .REGnn+1 + jmp ZVM_next +} + +Z80_instr_01: +Z80_LD_REGnn_nn REG_BC ; LD BC,nn +Z80_instr_11: +Z80_LD_REGnn_nn REG_DE ; LD DE,nn +Z80_instr_21: +Z80_LD_REGnn_nn REG_HL ; LD HL,nn +Z80_instr_31: +Z80_LD_REGnn_nn REG_SP ; LD SP,nn +Z80_instr_DD_21: +Z80_LD_REGnn_nn REG_IX ; LD IX,nn +Z80_instr_FD_21: +Z80_LD_REGnn_nn REG_IY ; LD IY,nn + !macro Z80_PUSH_REGnn .REGnn { lda .REGnn+1 jsr (VEC_store_stack) diff --git a/src/zvm_m65/z80_instr_load_8bit.s b/src/zvm_m65/z80_instr_load_8bit.s index ec3270f5..fdf14ce6 100644 --- a/src/zvm_m65/z80_instr_load_8bit.s +++ b/src/zvm_m65/z80_instr_load_8bit.s @@ -4,261 +4,60 @@ ; -; -; load register with other register -; - -Z80_instr_41: ; LD B,C - - lda REG_C - sta REG_B - jmp ZVM_next - -Z80_instr_42: ; LD B,D - - lda REG_D - sta REG_B - jmp ZVM_next - -Z80_instr_43: ; LD B,E - - lda REG_E - sta REG_B - jmp ZVM_next - -Z80_instr_44: ; LD B,H - - lda REG_H - sta REG_B - jmp ZVM_next - -Z80_instr_45: ; LD B,L - - lda REG_L - sta REG_B - jmp ZVM_next - -Z80_instr_47: ; LD B,A - - lda REG_A - sta REG_B - jmp ZVM_next - -Z80_instr_48: ; LD C,B - - lda REG_B - sta REG_C - jmp ZVM_next - -Z80_instr_4A: ; LD C,D - - lda REG_D - sta REG_C - jmp ZVM_next - -Z80_instr_4B: ; LD C,E - - lda REG_E - sta REG_C - jmp ZVM_next - -Z80_instr_4C: ; LD C,H - - lda REG_H - sta REG_C - jmp ZVM_next - -Z80_instr_4D: ; LD C,L - - lda REG_L - sta REG_C - jmp ZVM_next - -Z80_instr_4F: ; LD C,A - - lda REG_A - sta REG_C - jmp ZVM_next - -Z80_instr_50: ; LD D,B - - lda REG_B - sta REG_D - jmp ZVM_next - -Z80_instr_51: ; LD D,C - - lda REG_C - sta REG_D - jmp ZVM_next - -Z80_instr_53: ; LD D,E - - lda REG_E - sta REG_D - jmp ZVM_next - -Z80_instr_54: ; LD D,H - - lda REG_H - sta REG_D - jmp ZVM_next - -Z80_instr_55: ; LD D,L - - lda REG_L - sta REG_D - jmp ZVM_next - -Z80_instr_57: ; LD D,A - - lda REG_A - sta REG_D - jmp ZVM_next - -Z80_instr_58: ; LD E,B - - lda REG_B - sta REG_E - jmp ZVM_next - -Z80_instr_59: ; LD E,C - - lda REG_C - sta REG_E - jmp ZVM_next - -Z80_instr_5A: ; LD E,D - - lda REG_D - sta REG_E - jmp ZVM_next - -Z80_instr_5C: ; LD E,H - - lda REG_H - sta REG_E - jmp ZVM_next - -Z80_instr_5D: ; LD E,L - - lda REG_L - sta REG_E - jmp ZVM_next - -Z80_instr_5F: ; LD E,A - - lda REG_A - sta REG_E - jmp ZVM_next - -Z80_instr_60: ; LD H,B - - lda REG_B - sta REG_H - jmp ZVM_next - -Z80_instr_61: ; LD H,C - - lda REG_C - sta REG_H - jmp ZVM_next - -Z80_instr_62: ; LD H,D - - lda REG_D - sta REG_H - jmp ZVM_next - -Z80_instr_63: ; LD H,E - - lda REG_E - sta REG_H - jmp ZVM_next - -Z80_instr_65: ; LD H,L - - lda REG_L - sta REG_H - jmp ZVM_next - -Z80_instr_67: ; LD H,A - - lda REG_A - sta REG_H - rts - -Z80_instr_68: ; LD L,B - - lda REG_B - sta REG_L - jmp ZVM_next - -Z80_instr_69: ; LD L,C - - lda REG_C - sta REG_L - jmp ZVM_next - -Z80_instr_6A: ; LD L,D - - lda REG_D - sta REG_L - jmp ZVM_next - -Z80_instr_6B: ; LD L,E - - lda REG_E - sta REG_L - jmp ZVM_next - -Z80_instr_6C: ; LD L,H - - lda REG_H - sta REG_L - jmp ZVM_next - -Z80_instr_6F: ; LD L,A - - lda REG_A - sta REG_L - jmp ZVM_next - -Z80_instr_78: ; LD A,B - - lda REG_B - sta REG_A - jmp ZVM_next - -Z80_instr_79: ; LD A,C - - lda REG_C - sta REG_A - jmp ZVM_next - -Z80_instr_7A: ; LD A,D - - lda REG_D - sta REG_A - jmp ZVM_next - -Z80_instr_7B: ; LD A,E - - lda REG_E - sta REG_A - jmp ZVM_next - -Z80_instr_7C: ; LD A,H - - lda REG_H - sta REG_A - jmp ZVM_next - -Z80_instr_7D: ; LD A,L - - lda REG_L - sta REG_A +!macro Z80_LD_REGn_REGn .REGn1, .REGn2 { + lda .REGn2 + sta .REGn1 jmp ZVM_next +} + +Z80_instr_41: +Z80_LD_REGn_REGn REG_B, REG_C ; LD B,C +Z80_instr_42: +Z80_LD_REGn_REGn REG_B, REG_D ; LD B,D +Z80_instr_43: +Z80_LD_REGn_REGn REG_B, REG_E ; LD B,E +Z80_instr_44: +Z80_LD_REGn_REGn REG_B, REG_H ; LD B,H +Z80_instr_45: +Z80_LD_REGn_REGn REG_B, REG_L ; LD B,L +Z80_instr_47: +Z80_LD_REGn_REGn REG_B, REG_A ; LD B,A + +Z80_instr_48: +Z80_LD_REGn_REGn REG_C, REG_B ; LD C,B +Z80_instr_4A: +Z80_LD_REGn_REGn REG_C, REG_D ; LD C,D +Z80_instr_4B: +Z80_LD_REGn_REGn REG_C, REG_E ; LD C,E +Z80_instr_4C: +Z80_LD_REGn_REGn REG_C, REG_H ; LD C,H +Z80_instr_4D: +Z80_LD_REGn_REGn REG_C, REG_L ; LD C,L +Z80_instr_4F: +Z80_LD_REGn_REGn REG_C, REG_A ; LD C,A + +Z80_instr_50: +Z80_LD_REGn_REGn REG_D, REG_B ; LD D,B +Z80_instr_51: +Z80_LD_REGn_REGn REG_D, REG_C ; LD D,C +Z80_instr_53: +Z80_LD_REGn_REGn REG_D, REG_E ; LD D,E +Z80_instr_54: +Z80_LD_REGn_REGn REG_D, REG_H ; LD D,H +Z80_instr_55: +Z80_LD_REGn_REGn REG_D, REG_L ; LD D,L +Z80_instr_57: +Z80_LD_REGn_REGn REG_D, REG_A ; LD D,A + +Z80_instr_58: +Z80_LD_REGn_REGn REG_E, REG_B ; LD E,B +Z80_instr_59: +Z80_LD_REGn_REGn REG_E, REG_C ; LD E,C +Z80_instr_5A: +Z80_LD_REGn_REGn REG_E, REG_D ; LD E,D +Z80_instr_5C: +Z80_LD_REGn_REGn REG_E, REG_H ; LD E,H +Z80_instr_5D: +Z80_LD_REGn_REGn REG_E, REG_L ; LD E,L +Z80_instr_5F: +Z80_LD_REGn_REGn REG_E, REG_A ; LD E,A + +Z80_instr_60: +Z80_LD_REGn_REGn REG_H, REG_B ; LD H,B +Z80_instr_61: +Z80_LD_REGn_REGn REG_H, REG_C ; LD H,C +Z80_instr_62: +Z80_LD_REGn_REGn REG_H, REG_D ; LD H,D +Z80_instr_63: +Z80_LD_REGn_REGn REG_H, REG_E ; LD H,E +Z80_instr_65: +Z80_LD_REGn_REGn REG_H, REG_L ; LD H,L +Z80_instr_67: +Z80_LD_REGn_REGn REG_H, REG_A ; LD H,A + +Z80_instr_68: +Z80_LD_REGn_REGn REG_L, REG_B ; LD L,B +Z80_instr_69: +Z80_LD_REGn_REGn REG_L, REG_C ; LD L,C +Z80_instr_6A: +Z80_LD_REGn_REGn REG_L, REG_D ; LD L,D +Z80_instr_6B: +Z80_LD_REGn_REGn REG_L, REG_E ; LD L,E +Z80_instr_6C: +Z80_LD_REGn_REGn REG_L, REG_H ; LD L,H +Z80_instr_6F: +Z80_LD_REGn_REGn REG_L, REG_A ; LD L,A + +Z80_instr_78: +Z80_LD_REGn_REGn REG_A, REG_B ; LD A,B +Z80_instr_79: +Z80_LD_REGn_REGn REG_A, REG_C ; LD A,C +Z80_instr_7A: +Z80_LD_REGn_REGn REG_A, REG_D ; LD A,D +Z80_instr_7B: +Z80_LD_REGn_REGn REG_A, REG_E ; LD A,E +Z80_instr_7C: +Z80_LD_REGn_REGn REG_A, REG_H ; LD A,H +Z80_instr_7D: +Z80_LD_REGn_REGn REG_A, REG_L ; LD A,L ; ; load register with immediate value diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s index 22a72078..5c08f384 100644 --- a/src/zvm_m65/zvm_core.s +++ b/src/zvm_m65/zvm_core.s @@ -100,20 +100,16 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ; Z80_instr_DD_CB: ; #DDCB Z80_instr_FD_CB: ; #FDCB -Z80_instr_01: ; LD BC,nn Z80_instr_02: ; LD (BC),A Z80_instr_09: ; ADD HL,BC -Z80_instr_0A: ; LD A,(BC) -Z80_instr_11: ; LD DE,nn +Z80_instr_0A: ; LD A,(BC) Z80_instr_12: ; LD (DE),A Z80_instr_19: ; ADD HL,DE Z80_instr_1A: ; LD A,(DE) -Z80_instr_21: ; LD HL,nn Z80_instr_22: ; LD (nn),HL Z80_instr_27: ; DAA Z80_instr_29: ; ADD HL,HL Z80_instr_2A: ; LD HL,(nn) -Z80_instr_31: ; LD SP,nn Z80_instr_32: ; LD (nn),A Z80_instr_39: ; ADD HL,SP Z80_instr_3A: ; LD A,(nn) @@ -248,7 +244,6 @@ Z80_instr_CB_3E: ; SRL (HL) Z80_instr_CB_3F: ; SRL A Z80_instr_DD_09: ; ADD IX,BC Z80_instr_DD_19: ; ADD IX,DE -Z80_instr_DD_21: ; LD IX,nn Z80_instr_DD_22: ; LD (nn),IX Z80_instr_DD_29: ; ADD IX,IX Z80_instr_DD_2A: ; LD IX,(nn) @@ -311,7 +306,6 @@ Z80_instr_ED_BA: ; INDR Z80_instr_ED_BB: ; OTDR Z80_instr_FD_09: ; ADD IY,BC Z80_instr_FD_19: ; ADD IY,DE -Z80_instr_FD_21: ; LD IY,nn Z80_instr_FD_22: ; LD (nn),IY Z80_instr_FD_29: ; ADD IY,IY Z80_instr_FD_2A: ; LD IY,(nn)