From 690b2b832d15770178526665cb63da053a5aa67a Mon Sep 17 00:00:00 2001 From: FeralChild64 Date: Sat, 2 Jan 2021 19:52:02 +0100 Subject: [PATCH] some cleanup, mainly Z80 related --- src/basic/wedge/wedge_dos.s | 2 +- src/zvm_m65/,aliases_zvm.s | 100 ++++++++++++++++--------- src/zvm_m65/Z80_instr_shftrot_RL.s | 4 +- src/zvm_m65/Z80_instr_shftrot_RLC.s | 4 +- src/zvm_m65/Z80_instr_shftrot_RR.s | 4 +- src/zvm_m65/Z80_instr_shftrot_RRC.s | 4 +- src/zvm_m65/Z80_instr_shftrot_SLA.s | 4 +- src/zvm_m65/Z80_instr_shftrot_SLL.s | 4 +- src/zvm_m65/Z80_instr_shftrot_SRA.s | 4 +- src/zvm_m65/Z80_instr_shftrot_SRL.s | 4 +- src/zvm_m65/z80_instr_bit.s | 48 ++++++------ src/zvm_m65/z80_instr_block.s | 16 ++-- src/zvm_m65/z80_instr_call_return.s | 24 +++--- src/zvm_m65/z80_instr_io.s | 4 +- src/zvm_m65/z80_instr_jump.s | 6 +- src/zvm_m65/z80_instr_load_16bit.s | 12 +-- src/zvm_m65/z80_instr_load_8bit.s | 18 ++--- src/zvm_m65/z80_instr_math_8bit.s | 40 +++++----- src/zvm_m65/z80_instr_rotate_shift.s | 4 +- src/zvm_m65/z80_table_gen.s | 24 +----- src/zvm_m65/zvm_banking.s | 105 ++------------------------- src/zvm_m65/zvm_core.s | 25 +++---- 22 files changed, 190 insertions(+), 270 deletions(-) diff --git a/src/basic/wedge/wedge_dos.s b/src/basic/wedge/wedge_dos.s index 2059c1d2..099c0393 100644 --- a/src/basic/wedge/wedge_dos.s +++ b/src/basic/wedge/wedge_dos.s @@ -34,7 +34,7 @@ wedge_dos: ; Close all the channels, so that wedge has full control jsr JCLALL - ; Set file parameters, channel 15 is a typical one for commands + ; Set file parameters, channel 15 is a typical one for commands jsr SELDEV ; sets .X register lda #$0F ldy #$0F diff --git a/src/zvm_m65/,aliases_zvm.s b/src/zvm_m65/,aliases_zvm.s index 906527ba..101510df 100644 --- a/src/zvm_m65/,aliases_zvm.s +++ b/src/zvm_m65/,aliases_zvm.s @@ -77,37 +77,6 @@ ; $3E ; 2 bytes - reserved -; -; Memory banking vectors - every single routine destroys .Y in case of bank 0 -; - -; XXX inline some of these routines - provide separate opcode implementations for various banks - -!addr zvm_bankvectors__start = $40 - -!addr VEC_fetch_via_PC_inc = $40 ; fetch to .A from (PC), increment PC afterwards -!addr VEC_fetch_stack = $42 ; fetch to .A - stack POP operation -!addr VEC_store_stack = $44 ; store .A - stack PUSH operation, destroys .X - -; XXX implement routines for vectors below - -!addr VEC_fetch_via_BC = $46 -!addr VEC_store_via_BC = $48 -!addr VEC_fetch_via_DE = $4A -!addr VEC_store_via_DE = $4C -!addr VEC_fetch_via_HL = $4E -!addr VEC_store_via_HL = $50 -!addr VEC_fetch_via_IX_d = $52 -!addr VEC_fetch_via_IY_d = $54 -!addr VEC_store_via_IX_d = $56 -!addr VEC_store_via_IY_d = $58 -!addr VEC_fetch_via_nn = $5A -!addr VEC_store_via_nn = $5C -!addr VEC_fetch_via_plus1 = $5E -!addr VEC_store_via_plus1 = $60 ; XXX jump to next directly? -!addr VEC_xchng_stack_lo = $62 -!addr VEC_xchng_stack_hi = $64 - ; ; Constant/macros definitions ; @@ -145,8 +114,73 @@ !macro Z80_PUT_1_CF { smb0 REG_F } !macro Z80_PUT_0_CF { rmb0 REG_F } + ; -; Helper tables for CPU emulation, downwards from $2000 +; Macros to abstract memory access ; -!addr z80_atable_bank0 = $1FE0 ; table for bank 0 memory address conversion +!macro Z80_FETCH_VIA_PC_INC { ; fetch to .A from (PC), increment PC afterwards + + lda [REG_PC], z + inw REG_PC +} + +!macro Z80_FETCH_STACK { ; fetch to .A - stack POP operation + + lda [REG_SP], z + inw REG_SP +} + +!macro Z80_STORE_STACK { ; store .A - stack PUSH operation + + dew REG_SP + sta [REG_SP], z +} + +!macro Z80_FETCH_VIA_BC { ; fetch to .A from (BC) + + lda [REG_BC], z +} + +!macro Z80_STORE_VIA_BC { ; store .A to (BC) + + sta [REG_BC], z +} + +!macro Z80_FETCH_VIA_DE { ; fetch to .A from (DE) + + lda [REG_DE], z +} + +!macro Z80_STORE_VIA_DE { ; store .A to (DE) + + sta [REG_DE], z +} + +!macro Z80_FETCH_VIA_HL { ; fetch to .A from (HL) + + lda [REG_HL], z +} + +!macro Z80_STORE_VIA_HL { ; store .A to (HL) + + sta [REG_HL], z +} + +!macro Z80_STORE_BACK_VIA_HL { ; store .A to (HL) when instruction already used Z80_FETCH_VIA_HL + + sta [REG_HL], z +} + +; XXX turn vectors below into macros + +!addr VEC_fetch_via_IX_d = $52 +!addr VEC_fetch_via_IY_d = $54 +!addr VEC_store_via_IX_d = $56 +!addr VEC_store_via_IY_d = $58 +!addr VEC_fetch_via_nn = $5A +!addr VEC_store_via_nn = $5C +!addr VEC_fetch_via_plus1 = $5E +!addr VEC_store_via_plus1 = $60 ; XXX jump to next directly? +!addr VEC_xchng_stack_lo = $62 +!addr VEC_xchng_stack_hi = $64 diff --git a/src/zvm_m65/Z80_instr_shftrot_RL.s b/src/zvm_m65/Z80_instr_shftrot_RL.s index d775f526..26522ad7 100644 --- a/src/zvm_m65/Z80_instr_shftrot_RL.s +++ b/src/zvm_m65/Z80_instr_shftrot_RL.s @@ -18,7 +18,7 @@ !macro Z80_RL_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL clc bbr0 REG_F, @1 @@ -26,7 +26,7 @@ @1: rol - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_RL_VIA } diff --git a/src/zvm_m65/Z80_instr_shftrot_RLC.s b/src/zvm_m65/Z80_instr_shftrot_RLC.s index dcc2f17e..28ac47bc 100644 --- a/src/zvm_m65/Z80_instr_shftrot_RLC.s +++ b/src/zvm_m65/Z80_instr_shftrot_RLC.s @@ -18,7 +18,7 @@ !macro Z80_RLC_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL tax rol @@ -26,7 +26,7 @@ rol - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_RLC_VIA } diff --git a/src/zvm_m65/Z80_instr_shftrot_RR.s b/src/zvm_m65/Z80_instr_shftrot_RR.s index 03651ac4..d2a8a033 100644 --- a/src/zvm_m65/Z80_instr_shftrot_RR.s +++ b/src/zvm_m65/Z80_instr_shftrot_RR.s @@ -18,7 +18,7 @@ !macro Z80_RR_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL clc bbr0 REG_F, @1 @@ -26,7 +26,7 @@ @1: ror - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_RR_VIA } diff --git a/src/zvm_m65/Z80_instr_shftrot_RRC.s b/src/zvm_m65/Z80_instr_shftrot_RRC.s index 2c0373c1..05bf84b1 100644 --- a/src/zvm_m65/Z80_instr_shftrot_RRC.s +++ b/src/zvm_m65/Z80_instr_shftrot_RRC.s @@ -18,7 +18,7 @@ !macro Z80_RRC_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL tax ror @@ -26,7 +26,7 @@ ror - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_RRC_VIA } diff --git a/src/zvm_m65/Z80_instr_shftrot_SLA.s b/src/zvm_m65/Z80_instr_shftrot_SLA.s index b0e6a624..5f8c136b 100644 --- a/src/zvm_m65/Z80_instr_shftrot_SLA.s +++ b/src/zvm_m65/Z80_instr_shftrot_SLA.s @@ -14,10 +14,10 @@ !macro Z80_SLA_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL asl - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_SLA_VIA } diff --git a/src/zvm_m65/Z80_instr_shftrot_SLL.s b/src/zvm_m65/Z80_instr_shftrot_SLL.s index a93d9e78..8be6b621 100644 --- a/src/zvm_m65/Z80_instr_shftrot_SLL.s +++ b/src/zvm_m65/Z80_instr_shftrot_SLL.s @@ -15,11 +15,11 @@ !macro Z80_SLL_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL sec rol - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_SLL_VIA } diff --git a/src/zvm_m65/Z80_instr_shftrot_SRA.s b/src/zvm_m65/Z80_instr_shftrot_SRA.s index a36781e7..5c0722d4 100644 --- a/src/zvm_m65/Z80_instr_shftrot_SRA.s +++ b/src/zvm_m65/Z80_instr_shftrot_SRA.s @@ -18,7 +18,7 @@ !macro Z80_SRA_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL tax ror @@ -26,7 +26,7 @@ ror - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_SRA_VIA } diff --git a/src/zvm_m65/Z80_instr_shftrot_SRL.s b/src/zvm_m65/Z80_instr_shftrot_SRL.s index 514ea3c3..12e748b4 100644 --- a/src/zvm_m65/Z80_instr_shftrot_SRL.s +++ b/src/zvm_m65/Z80_instr_shftrot_SRL.s @@ -15,11 +15,11 @@ !macro Z80_SRL_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL clc ror - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_SRL_VIA } diff --git a/src/zvm_m65/z80_instr_bit.s b/src/zvm_m65/z80_instr_bit.s index 5cdfb9b1..3c939fd4 100644 --- a/src/zvm_m65/z80_instr_bit.s +++ b/src/zvm_m65/z80_instr_bit.s @@ -360,56 +360,56 @@ Z80_common_bit7_1: Z80_instr_CB_46: ; BIT 0,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%00000001 bne Z80_common_bitHL_1 bra Z80_common_bitHL_0 Z80_instr_CB_4E: ; BIT 1,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%00000010 bne Z80_common_bitHL_1 bra Z80_common_bitHL_0 Z80_instr_CB_56: ; BIT 2,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%00000100 bne Z80_common_bitHL_1 bra Z80_common_bitHL_0 Z80_instr_CB_5E: ; BIT 3,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%00001000 bne Z80_common_bitHL_1 bra Z80_common_bitHL_0 Z80_instr_CB_66: ; BIT 4,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%00010000 bne Z80_common_bitHL_1 bra Z80_common_bitHL_0 Z80_instr_CB_6E: ; BIT 5,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%00100000 bne Z80_common_bitHL_1 bra Z80_common_bitHL_0 Z80_instr_CB_76: ; BIT 6,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%01000000 bne Z80_common_bitHL_1 bra Z80_common_bitHL_0 Z80_instr_CB_7E: ; BIT 7,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%10000000 beq Z80_common_bitHL_0 @@ -872,49 +872,49 @@ Z80_instr_CB_FF: ; SET 7,A Z80_instr_CB_C6: ; SET 0,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL ora #%00000001 jmp ZVM_store_via_HL_next Z80_instr_CB_CE: ; SET 1,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL ora #%00000010 jmp ZVM_store_via_HL_next Z80_instr_CB_D6: ; SET 2,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL ora #%00000100 jmp ZVM_store_via_HL_next Z80_instr_CB_DE: ; SET 3,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL ora #%00001000 jmp ZVM_store_via_HL_next Z80_instr_CB_E6: ; SET 4,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL ora #%00010000 jmp ZVM_store_via_HL_next Z80_instr_CB_EE: ; SET 5,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL ora #%00100000 jmp ZVM_store_via_HL_next Z80_instr_CB_F6: ; SET 6,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL ora #%01000000 jmp ZVM_store_via_HL_next Z80_instr_CB_FE: ; SET 7,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL ora #%10000000 jmp ZVM_store_via_HL_next @@ -1256,49 +1256,49 @@ Z80_instr_CB_BF: ; RES 7,A Z80_instr_CB_86: ; RES 0,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%11111110 jmp ZVM_store_via_HL_next Z80_instr_CB_8E: ; RES 1,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%11111101 jmp ZVM_store_via_HL_next Z80_instr_CB_96: ; RES 2,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%11111011 jmp ZVM_store_via_HL_next Z80_instr_CB_9E: ; RES 3,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%11110111 jmp ZVM_store_via_HL_next Z80_instr_CB_A6: ; RES 4,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%11101111 jmp ZVM_store_via_HL_next Z80_instr_CB_AE: ; RES 5,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%11011111 jmp ZVM_store_via_HL_next Z80_instr_CB_B6: ; RES 6,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%10111111 jmp ZVM_store_via_HL_next Z80_instr_CB_BE: ; RES 7,(HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL and #%01111111 jmp ZVM_store_via_HL_next diff --git a/src/zvm_m65/z80_instr_block.s b/src/zvm_m65/z80_instr_block.s index a0e3274e..49e2733f 100644 --- a/src/zvm_m65/z80_instr_block.s +++ b/src/zvm_m65/z80_instr_block.s @@ -10,8 +10,8 @@ Z80_instr_ED_A0: ; LDI and #($FF - Z80_HF - Z80_PF - Z80_NF) sta REG_F - jsr (VEC_fetch_via_HL) - jsr (VEC_store_via_DE) + +Z80_FETCH_VIA_HL + +Z80_STORE_VIA_DE inw REG_HL inw REG_DE @@ -27,8 +27,8 @@ Z80_instr_ED_B0: ; LDIR and #($FF - Z80_HF - Z80_PF - Z80_NF) sta REG_F @1: - jsr (VEC_fetch_via_HL) - jsr (VEC_store_via_DE) + +Z80_FETCH_VIA_HL + +Z80_STORE_VIA_DE inw REG_HL inw REG_DE @@ -43,8 +43,8 @@ Z80_instr_ED_A8: ; LDD and #($FF - Z80_HF - Z80_PF - Z80_NF) sta REG_F - jsr (VEC_fetch_via_HL) - jsr (VEC_store_via_DE) + +Z80_FETCH_VIA_HL + +Z80_STORE_VIA_DE dew REG_HL dew REG_DE @@ -60,8 +60,8 @@ Z80_instr_ED_B8: ; LDDR and #($FF - Z80_HF - Z80_PF - Z80_NF) sta REG_F @1: - jsr (VEC_fetch_via_HL) - jsr (VEC_store_via_DE) + +Z80_FETCH_VIA_HL + +Z80_STORE_VIA_DE dew REG_HL dew REG_DE diff --git a/src/zvm_m65/z80_instr_call_return.s b/src/zvm_m65/z80_instr_call_return.s index 63f3c836..620d22d8 100644 --- a/src/zvm_m65/z80_instr_call_return.s +++ b/src/zvm_m65/z80_instr_call_return.s @@ -6,19 +6,19 @@ Z80_instr_CD: ; CALL nn - jsr (VEC_fetch_via_PC_inc) - pha - jsr (VEC_fetch_via_PC_inc) - pha + +Z80_FETCH_VIA_PC_INC + tax + +Z80_FETCH_VIA_PC_INC + tay lda REG_PC+1 - jsr (VEC_store_stack) + +Z80_STORE_STACK lda REG_PC+0 - jsr (VEC_store_stack) + +Z80_STORE_STACK - pla + tya sta REG_PC+1 - pla + txa sta REG_PC+0 jmp ZVM_next @@ -92,9 +92,9 @@ Z80_illeg_ED_7D: ; RETN Z80_instr_ED_4D: ; RETTI Z80_instr_C9: ; RET - jsr (VEC_fetch_stack) + +Z80_FETCH_STACK sta REG_PC+0 - jsr (VEC_fetch_stack) + +Z80_FETCH_STACK sta REG_PC+1 jmp ZVM_next @@ -142,9 +142,9 @@ Z80_instr_F8: ; RET M !macro Z80_RST .P { lda REG_PC+1 - jsr (VEC_store_stack) + +Z80_STORE_STACK lda REG_PC+0 - jsr (VEC_store_stack) + +Z80_STORE_STACK lda #$00 sta REG_PC+1 lda #.P diff --git a/src/zvm_m65/z80_instr_io.s b/src/zvm_m65/z80_instr_io.s index d1ed76b2..eb407124 100644 --- a/src/zvm_m65/z80_instr_io.s +++ b/src/zvm_m65/z80_instr_io.s @@ -8,7 +8,7 @@ Z80_instr_DB: ; IN A,(n) - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC sta ADDR_IO+0 lda REG_A sta ADDR_IO+1 @@ -56,7 +56,7 @@ Z80_illeg_ED_70: +Z80_IN_NULL ; Z80_instr_D3: ; OUT (n),A - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC sta ADDR_IO+0 lda REG_A sta ADDR_IO+1 diff --git a/src/zvm_m65/z80_instr_jump.s b/src/zvm_m65/z80_instr_jump.s index f6e6f009..47729310 100644 --- a/src/zvm_m65/z80_instr_jump.s +++ b/src/zvm_m65/z80_instr_jump.s @@ -6,9 +6,9 @@ Z80_instr_C3: ; JP nn - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC sta REG_PC+0 - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC sta REG_PC+1 jmp ZVM_next @@ -102,7 +102,7 @@ Z80_instr_18: ; JR e @1: rmb7 REG_PC+0 @2: - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC tax lda z80_otable_displacement,x clc diff --git a/src/zvm_m65/z80_instr_load_16bit.s b/src/zvm_m65/z80_instr_load_16bit.s index d4560f11..e7fb9dbb 100644 --- a/src/zvm_m65/z80_instr_load_16bit.s +++ b/src/zvm_m65/z80_instr_load_16bit.s @@ -5,9 +5,9 @@ !macro Z80_LD_REGnn_nn .REGnn { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC sta .REGnn+0 - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC sta .REGnn+1 jmp ZVM_next } @@ -65,9 +65,9 @@ Z80_instr_ED_7B: +Z80_LD_REGnn_VIA_nn REG_SP ; !macro Z80_PUSH_REGnn .REGnn { lda .REGnn+1 - jsr (VEC_store_stack) + +Z80_STORE_STACK lda .REGnn+0 - jsr (VEC_store_stack) + +Z80_STORE_STACK jmp ZVM_next } @@ -79,9 +79,9 @@ Z80_instr_DD_E5: +Z80_PUSH_REGnn REG_IX ; Z80_instr_FD_E5: +Z80_PUSH_REGnn REG_IY ; PUSH IY !macro Z80_POP_REGnn .REGnn { - jsr (VEC_fetch_stack) + +Z80_FETCH_STACK sta .REGnn+0 - jsr (VEC_fetch_stack) + +Z80_FETCH_STACK lda .REGnn+1 jmp ZVM_next } diff --git a/src/zvm_m65/z80_instr_load_8bit.s b/src/zvm_m65/z80_instr_load_8bit.s index 90e640d4..08c42fbc 100644 --- a/src/zvm_m65/z80_instr_load_8bit.s +++ b/src/zvm_m65/z80_instr_load_8bit.s @@ -110,7 +110,7 @@ Z80_illeg_FD_6C: +Z80_LD_REGn_REGn REG_IYL, REG_IYH ; Z80_illeg_FD_6F: +Z80_LD_REGn_REGn REG_IYL, REG_A ; LD IYL,A !macro Z80_LD_REGn_n .REGn { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC sta .REGn jmp ZVM_next } @@ -129,7 +129,7 @@ Z80_illeg_FD_26: +Z80_LD_REGn_n REG_IYH ; Z80_illeg_FD_2E: +Z80_LD_REGn_n REG_IYL ; LD IYL,n !macro Z80_LD_REGn_VIA_HL .REGn { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL sta .REGn jmp ZVM_next } @@ -144,7 +144,7 @@ Z80_instr_7E: +Z80_LD_REGn_VIA_HL REG_A ; !macro Z80_LD_VIA_HL_REGn .REGn { lda .REGn - jsr (VEC_store_via_HL) + +Z80_STORE_VIA_HL jmp ZVM_next } @@ -159,24 +159,24 @@ Z80_instr_77: +Z80_LD_VIA_HL_REGn REG_A ; Z80_instr_02: ; LD (BC),A lda REG_A - jsr (VEC_store_via_BC) + +Z80_STORE_VIA_BC jmp ZVM_next Z80_instr_0A: ; LD A,(BC) - jsr (VEC_fetch_via_BC) + +Z80_FETCH_VIA_BC sta REG_A jmp ZVM_next Z80_instr_12: ; LD (DE),A lda REG_A - jsr (VEC_store_via_DE) + +Z80_STORE_VIA_DE jmp ZVM_next Z80_instr_1A: ; LD A,(DE) - jsr (VEC_fetch_via_DE) + +Z80_FETCH_VIA_DE sta REG_A jmp ZVM_next @@ -250,8 +250,8 @@ Z80_instr_FD_77: +Z80_LD_VIA_IY_d_REG_n REG_A ; Z80_instr_36: ; LD (HL),n - jsr (VEC_fetch_via_PC_inc) - jsr (VEC_store_via_HL) + +Z80_FETCH_VIA_PC_INC + +Z80_STORE_VIA_HL jmp ZVM_next Z80_instr_ED_57: ; LD A,I diff --git a/src/zvm_m65/z80_instr_math_8bit.s b/src/zvm_m65/z80_instr_math_8bit.s index aed06ac6..a7a11f09 100644 --- a/src/zvm_m65/z80_instr_math_8bit.s +++ b/src/zvm_m65/z80_instr_math_8bit.s @@ -8,12 +8,12 @@ !macro Z80_ADD_n { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC bra Z80_common_add } !macro Z80_ADC_n { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC bbs0 REG_F,Z80_common_adc jmp Z80_common_add } @@ -30,12 +30,12 @@ } !macro Z80_ADD_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL bra Z80_common_add } !macro Z80_ADC_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL bbs0 REG_F,Z80_common_adc jmp Z80_common_add } @@ -167,12 +167,12 @@ Z80_common_adc: jmp ZVM_next !macro Z80_SUB_n { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC bra Z80_common_sub } !macro Z80_SBC_n { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC bbs0 REG_F,Z80_common_sbc jmp Z80_common_sub } @@ -189,12 +189,12 @@ Z80_common_adc: } !macro Z80_SUB_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL bra Z80_common_sub } !macro Z80_SBC_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL bbs0 REG_F,Z80_common_sbc jmp Z80_common_sub } @@ -326,7 +326,7 @@ Z80_common_sbc: jmp ZVM_next !macro Z80_CP_n { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC bra Z80_common_cp } @@ -336,7 +336,7 @@ Z80_common_sbc: } !macro Z80_CP_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL bra Z80_common_cp } @@ -426,12 +426,12 @@ Z80_common_cp: } !macro Z80_AND_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL +Z80_AND_common } !macro Z80_AND_n { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC +Z80_AND_common } @@ -486,12 +486,12 @@ Z80_instr_FD_A6: +Z80_AND_VIA_IY_d ; } !macro Z80_OR_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL +Z80_OR_common } !macro Z80_OR_n { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC +Z80_OR_common } @@ -543,12 +543,12 @@ Z80_instr_FD_B6: +Z80_OR_VIA_IY_d ; } !macro Z80_XOR_VIA_HL { - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL +Z80_XOR_common } !macro Z80_XOR_n { - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC +Z80_XOR_common } @@ -612,10 +612,10 @@ Z80_common_INC: Z80_instr_34: ; INC (HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL tax inc - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_INC Z80_instr_DD_34: ; INC (IX+d) @@ -668,10 +668,10 @@ Z80_common_DEC: Z80_instr_35: ; DEC (HL) - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL tax dec - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL bra Z80_common_DEC Z80_instr_DD_35: ; DEC (IX+d) diff --git a/src/zvm_m65/z80_instr_rotate_shift.s b/src/zvm_m65/z80_instr_rotate_shift.s index b38219c4..d1233f9a 100644 --- a/src/zvm_m65/z80_instr_rotate_shift.s +++ b/src/zvm_m65/z80_instr_rotate_shift.s @@ -8,7 +8,7 @@ Z80_instr_ED_67: ; RRD - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL sta REG_TMP1 lda REG_A @@ -47,7 +47,7 @@ Z80_instr_ED_67: ; RRD Z80_instr_ED_6F: ; RLD - jsr (VEC_fetch_via_HL) + +Z80_FETCH_VIA_HL sta REG_TMP1 lda REG_A diff --git a/src/zvm_m65/z80_table_gen.s b/src/zvm_m65/z80_table_gen.s index 989825ea..5bce535d 100644 --- a/src/zvm_m65/z80_table_gen.s +++ b/src/zvm_m65/z80_table_gen.s @@ -9,35 +9,13 @@ z80_table_gen: !pet $0D, "Generating CPU tables... " !byte 0 - ; - ; Generating: z80_atable_bank0 - ; Dependencies: NONE - ; Destroys: NONE - ; - - ldx #$00 - -@loop_atable_bank0: - - lda #$04 ; $0000-$DFFF maps to $40000-$4DFFF (bank 0 RAM) - cpx #$E0 - bcc @loop_atable_bank0_gotit - inc ; $E000-$FFFF maps to $5E000-$5FFFF (common RAM) - -@loop_atable_bank0_gotit: - - sta z80_atable_bank0, x - - inx - bne @loop_atable_bank0 - ; ; Generating: XXX ; Dependencies: NONE ; Destroys: NONE ; - ; XXX add more tables here + ; XXX add table generators ; ; The END diff --git a/src/zvm_m65/zvm_banking.s b/src/zvm_m65/zvm_banking.s index c6c90590..196b0738 100644 --- a/src/zvm_m65/zvm_banking.s +++ b/src/zvm_m65/zvm_banking.s @@ -3,23 +3,6 @@ ; Z80 Virtual Machine banking support ; - -ZVM_bank0_vectab: - - !word ZVM_bank0_fetch_via_PC_inc - !word ZVM_bank0_fetch_stack - !word ZVM_bank0_store_stack - - ; XXX add remaining routines here - -ZVM_bank1_vectab: - - !word ZVM_bank1_fetch_via_PC_inc - !word ZVM_bank1_fetch_stack - !word ZVM_bank1_store_stack - - ; XXX add remaining routines here - ; ; Bank switching routines ; @@ -29,22 +12,24 @@ ZVM_set_bank_0: lda #$00 sta BANK_ID - ; XXX use DMAgic to switch banks (vectors on zeropage) + ; XXX use DMAgic to copy common memory - rts + lda #$04 + bra ZVM_set_bank_common ZVM_set_bank_1: lda #$01 sta BANK_ID - ; XXX use DMAgic to switch banks (vectors on zeropage) - - ; Since all the Z80 bank 1 memory is located in $0005:$xxxx, - ; we can set bytes in certain pointers for faster execution + ; XXX use DMAgic to copy common memory lda #$05 + ; FALLTROUGH + +ZVM_set_bank_common: + sta REG_BC_EXT sta REG_DE_EXT sta REG_HL_EXT @@ -55,77 +40,3 @@ ZVM_set_bank_1: sta PTR_DATA+2 rts - -; -; Memory access routines -; - -ZVM_bank0_fetch_via_PC_inc: - - ldy REG_PC+1 - lda z80_atable_bank0,y - sta REG_PC_EXT+0 - - ; FALLTROUGH - -ZVM_bank1_fetch_via_PC_inc: - - lda [REG_PC], z - inw REG_PC - - rts - -ZVM_bank0_fetch_stack: - - ldy REG_SP+1 - lda z80_atable_bank0,y - sta REG_PC_EXT - - ; FALLTROUGH - -ZVM_bank1_fetch_stack: - - lda [REG_SP], z - inw REG_SP - - rts - -ZVM_bank0_store_stack: - - dew REG_SP - - ldy REG_SP+1 - ldx z80_atable_bank0,y - stx REG_SP_EXT - - sta [PTR_DATA], z - - rts - -ZVM_bank1_store_stack: - - dew REG_SP - sta [REG_SP], z - - rts - - - - - - -; XXX cleanup code below - - - -ZVM_fetch_IO: - - ; XXX fetch addresses via ADDR_IO - but which ones are safe? Should we have a whitelist? - lda #$00 - sta REG_A - rts - -ZVM_store_IO: - - ; XXX again, we should have a whitelist of addresses - rts diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s index c9d6ef58..15827c2b 100644 --- a/src/zvm_m65/zvm_core.s +++ b/src/zvm_m65/zvm_core.s @@ -72,7 +72,7 @@ ZVM_entry: ZVM_store_via_HL_next: - sta [REG_HL],z + +Z80_STORE_BACK_VIA_HL ; FALLTROUGH @@ -80,7 +80,7 @@ ZVM_store_via_HL_next: ; Fetch and execute next opcode - jsr (VEC_fetch_via_PC_inc) + +Z80_FETCH_VIA_PC_INC asl tax bcs @1 @@ -155,22 +155,19 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ; +; XXX cleanup code below +ZVM_fetch_IO: + ; XXX fetch addresses via ADDR_IO - but which ones are safe? Should we have a whitelist? + lda #$00 + sta REG_A + rts +ZVM_store_IO: - - - - - - - - - - - - + ; XXX again, we should have a whitelist of addresses + rts