LOAD/SAVE preparation routines should be OK now

2019-10-29 22:15:44 +01:00
1 parent 7eca8ea05b
commit 73f1e24e3c
@@ -1,11 +1,22 @@

+//
+// LOAD preparation routine
+//
+
+//
+// Input (according to http://sta.c64.org/cbm64krnfunc.html)
+// .A        - 0 for load, non-0 for verify
+// .X and .Y - load address (if secondary address is 0)
+//
+
 //
 // Note: Although the vector at $330 points to $F4A5, the Kernal jump table points to $F49E
 // (see also Mapping the C64, page 76). By experimenting I have discovered that $F49E performs
 // indirect jump via ($0330) vector, after setting MEMUSS.
 //

-LOAD_INT:
+
+LOAD_PREP:

 	sty MEMUSS+1
 	stx MEMUSS+0
@@ -1,12 +0,0 @@
-
-//
-// XXX Note: something unusual was done with LOAD routine - although the vector at $330 points to $F4A5,
-//           the Kernal jump table points to $F49E (see also Mapping the C64, page 76). By experimenting
-//           I have already discovered that $F4A5 performs indirect jump via ($0330) vector, but it must
-//           be doing a little bit more - not sure yet, what. Something similar is done with SAVE.
-//
-//           This has to be clarified.
-//
-
-SAVE_INT:
-    jmp (ISAVE)
@@ -0,0 +1,29 @@
+
+//
+// SAVE preparation routine
+//
+
+//
+// Input (according to http://sta.c64.org/cbm64krnfunc.html)
+// .A        - address of zero page register holding start address of memory area to save
+// .X and .Y - end address of memory area plus 1
+//
+
+//
+// Note: Experimenting can easily confirm that SAVE preparation routine does similar
+// actions as LOAD preparation routine.
+//
+
+SAVE_PREP:
+
+	sty EAL+1
+	stx EAL+0
+
+	tax
+
+	lda $01, x
+	sta STAL+1
+	lda $00, x
+	sta STAL+0
+
+    jmp (ISAVE)
@@ -1,4 +1,4 @@
 // load RAM from a device
 // C64 Programmer's Reference Guide Page 272

-	jmp LOAD_INT
+	jmp LOAD_PREP
@@ -1,4 +1,4 @@
 // SAVE RAM to device
 // C64 Programmer's Reference Guide Page 273

-	jmp SAVE_INT
+	jmp SAVE_PREP