more sane directory name, updated binaries
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@@ -0,0 +1,36 @@
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// #LAYOUT# STD * #TAKE
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// #LAYOUT# * KERNAL_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// Advertise burst IEC protocol support to the receiver
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//
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//
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// Based on idea by Pasi 'Albert' Ojala and description from
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// https://sites.google.com/site/h2obsession/CBM/C128/fast-serial-for-uiec
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//
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#if CONFIG_IEC_BURST_CIA1
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burst_advertise:
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#if CONFIG_IEC_JIFFYDOS
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// Skip if other protocol (only JiffyDOS is possible at this moment) already detected
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lda IECPROTO
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bmi !+
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bne burst_advertise_done
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!:
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#endif
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panic #$FF // XXX implement this
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burst_advertise_done:
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rts
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#endif
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@@ -0,0 +1,60 @@
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// #LAYOUT# STD * #TAKE
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// #LAYOUT# * KERNAL_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// Advertise burst IEC protocol support to the receiver
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//
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//
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// Based on idea by Pasi 'Albert' Ojala and description from
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// https://sites.google.com/site/h2obsession/CBM/C128/fast-serial-for-uiec
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//
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#if CONFIG_IEC_BURST_CIA2
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burst_advertise:
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#if CONFIG_IEC_JIFFYDOS
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// Skip if other protocol (only JiffyDOS is possible at this moment) already detected
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lda IECPROTO
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bmi !+
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bne burst_advertise_done
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!:
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#endif
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// Make sure this is not done under ATN
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jst iec_release_atn
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// Set the clock rate to the fastest possible
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ldy #$01
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sty CIA2_TIMALO
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dey
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sty CIA2_TIMAHI
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// Prepare registers for transfer
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lda #$C1
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sta CIA2_CRA // start timer A, serial out, TOD 50Hz
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bit CIA2_ICR // clear interrupt register
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// Send test byte
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lda #$FF // $FF keeps DATA released, see https://www.c64-wiki.com/wiki/Fast_serial_bus_protocol
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sta CIA2_SDR
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// Wait until byte sent
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lda #$08 // interrupt mask
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!:
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bit CIA2_ICR
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beq !-
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// FALLTROUGH
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burst_advertise_done:
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rts
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#endif
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@@ -0,0 +1,31 @@
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// #LAYOUT# STD * #TAKE
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// #LAYOUT# * KERNAL_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// Advertise burst IEC protocol support to the receiver
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//
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#if CONFIG_IEC_BURST_MEGA_65
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burst_advertise:
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#if CONFIG_IEC_JIFFYDOS
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// Skip if other protocol (only JiffyDOS is possible at this moment) already detected
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lda IECPROTO
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bmi !+
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bne burst_advertise_done:
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!:
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#endif
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panic #$FF // XXX implement this
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burst_advertise_done:
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rts
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#endif
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@@ -0,0 +1,65 @@
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// #LAYOUT# STD * #TAKE
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// #LAYOUT# * KERNAL_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// Helper routine for JiffyDOS detection
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//
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// The standard parallel cable (used by SpeedDOS, DolphinDOS 2, etc.) connects the following UserPort lines:
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// - PB0-PB7 - CIA2_PRB ($DD01), CIA #2 port B
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// - PC2, FLAG2 - CIA2_ICR ($DD0D), CIA #2 handshaking line
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//
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// See:
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// - http://sta.c64.org/cbmpar41c.html
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// - http://sta.c64.org/cbmpar71c.html
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// - Commodore 64 Programers Referencee Guide, pages 360-361, 429
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// - Computes Mapping the C64, page 183
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#if CONFIG_IEC_DOLPHINDOS
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dolphindos_detect:
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// Make sure the port settings are correct
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lda #$7F
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sta CIA2_ICR // disable interrupt generation
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lda #$00
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sta CIA2_DDRB // set all port B lines as input
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// According to logs collected from modified VICE emulator, original DolphinDOS ROM
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// constantly reads $DD0D and $DD01 until handshake bit of $DD0D is set, or some kind
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// of timeout occurs
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ldx #$20
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dolphindos_detect_loop:
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lda CIA2_ICR
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cmp #$10
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beq dolphindos_detect_success
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lda CIA2_PRB // XXX do we need this read?
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dex
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bne dolphindos_detect_loop
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// FALLTROUGH - protocol not detected
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dolphindos_detect_fail:
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rts
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dolphindos_detect_success:
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// Protocol detected
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lda #$02
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sta IECPROTO
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rts
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#endif // CONFIG_IEC_DOLPHINDOS
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@@ -0,0 +1,122 @@
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// #LAYOUT# STD * #TAKE
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// #LAYOUT# * KERNAL_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// DolphinDOS protocol support for IEC - optimized load loop
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//
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#if CONFIG_IEC_DOLPHINDOS && !CONFIG_MEMORY_MODEL_60K
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dolphindos_load:
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// Timing is critical for some parts, do not allow interrupts
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sei
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// A trick to shorten EAL update time
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ldy #$00
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#if CONFIG_IEC_DOLPHINDOS_FAST
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// Another trick: prepare values for quickly setting/releasing DATA
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lda CIA2_PRA
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and #$FF - BIT_CIA2_PRA_DAT_OUT - BIT_CIA2_PRA_CLK_OUT - BIT_CIA2_PRA_ATN_OUT
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sta IECPROTO // release DATA
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ora #BIT_CIA2_PRA_DAT_OUT
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sta TBTCNT // pull DATA
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#endif
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// FALLTROUGH
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dolphindos_load_loop:
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#if !CONFIG_IEC_DOLPHINDOS_FAST
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// Check if this was EOI
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bit IOSTATUS
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bvs dolphindos_load_end
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#endif
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// Wait for the talker to release the CLK line
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!:
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bit CIA2_PRA
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bvc !-
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// Release the DATA to signal we are ready
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#if !CONFIG_IEC_DOLPHINDOS_FAST
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lda CIA2_PRA
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and #$FF - BIT_CIA2_PRA_DAT_OUT // release
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#else
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lda IECPROTO
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#endif
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sta CIA2_PRA
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#if !CONFIG_IEC_DOLPHINDOS_FAST
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// Check if EOI
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jsr iec_rx_check_eoi // can damage .X, but this is safe
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#else
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// Check if EOI - inlined code to avoid wasting cycles on RTS
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ldx #$13
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!:
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bit CIA2_PRA
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bvc dolphindos_load_no_eoi
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dex
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bne !-
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// EOI - mark it and retrieve the last byte
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jsr iec_rx_check_eoi_confirm
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lda CIA2_PRB
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sta (EAL),y
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// Update EAL for the last time
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sec
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jsr iec_update_EAL_by_Y
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// Restore proper IECPROTO value
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lda #$02
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sta IECPROTO
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// End of load loop
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jmp load_iec_loop_end
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dolphindos_load_no_eoi:
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#endif
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// Retrieve and store byte
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lda CIA2_PRB
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sta (EAL),y
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// Pull DATA to acknowledge
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#if !CONFIG_IEC_DOLPHINDOS_FAST
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lda CIA2_PRA
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ora #BIT_CIA2_PRA_DAT_OUT
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#else
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lda TBTCNT
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#endif
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sta CIA2_PRA
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// Handle EAL
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iny
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bne dolphindos_load_loop
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inc EAL+1
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jmp dolphindos_load_loop
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#if !CONFIG_IEC_DOLPHINDOS_FAST
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dolphindos_load_end:
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// Update EAL
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clc
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jsr iec_update_EAL_by_Y
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// End of load loop
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jmp load_iec_loop_end
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#endif
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#endif // CONFIG_IEC_DOLPHINDOS and not CONFIG_MEMORY_MODEL_60K
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@@ -0,0 +1,42 @@
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// #LAYOUT# STD * #TAKE
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// #LAYOUT# * KERNAL_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// Helper table for encoding lower nibble for JiffyDOS,
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// values found by observing the actual transfer using
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// original ROMs
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//
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// Similar tables are probably used by nearly all the disk turbo loaders,
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// either on the C64 or drive side, soometimes generated in RAM on the fly;
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// example disk turbo presented below has a very similar table - but the
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// values are in reversed order:
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// - https://www.pagetable.com/?p=568
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#if CONFIG_IEC_JIFFYDOS
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jiffydos_bittable:
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.byte $00
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.byte $80 // $10 + $70
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.byte $20
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.byte $A0 // $30 + $70
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.byte $40
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.byte $C0 // $50 + $70
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.byte $60
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.byte $E0 // $70 + $70
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.byte $10 // $80 - $70
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.byte $90
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.byte $30 // $A0 - $70
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.byte $B0
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.byte $50 // $C0 - $70
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.byte $D0
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.byte $70 // $E0 - $70
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.byte $F0
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#endif // CONFIG_IEC_JIFFYDOS
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@@ -0,0 +1,54 @@
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// #LAYOUT# STD * #TAKE
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// #LAYOUT# * KERNAL_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// Helper routine for JiffyDOS detection
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//
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// Detection is done by inserting a long delay (above 400us?) during sending command last bit, see:
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// - https://sites.google.com/site/h2obsession/CBM/C128/JiffySoft128
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// - https://github.com/rkrajnc/sd2iec/blob/master/src/iec.c
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// The 'iec.s' suggests, that the drive should respond by pulling data
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// The original JiffyDOS ROM seems to perform detection with every command
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// (even though for many of them it always fails) and we have to replicate
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// this behaviour for compatibility with at least 1541 JiffyDOS ROM
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#if CONFIG_IEC_JIFFYDOS
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jiffydos_detect:
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ldy #$25 // 400us is nearly 410 cycles on NTSC
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// loop iteration below is 11 cycles,
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// and several cycles were already used
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jiffydos_detect_loop:
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lda CIA2_PRA // 4 cycles
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bpl jiffydos_detected // 2 cycles
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dey // 2 cycles
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bne jiffydos_detect_loop // 3 cycles if branch
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lda IECPROTO
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bpl jiffydos_detect_end // no detection requested, preserve existing protocol
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lda #$00 // normal protocol
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beq jiffydos_store_proto // branch always
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jiffydos_detected:
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jsr iec_wait_for_data_release // guessed from VICE logs
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lda #$01 // JiffyDOS protocol
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// FALLTROUGH
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jiffydos_store_proto:
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sta IECPROTO
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// FALLTROUGH
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jiffydos_detect_end:
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rts
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#endif // CONFIG_IEC_JIFFYDOS
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@@ -0,0 +1,175 @@
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// #LAYOUT# STD * #TAKE
|
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// #LAYOUT# * KERNAL_0 #TAKE
|
||||
// #LAYOUT# * * #IGNORE
|
||||
|
||||
//
|
||||
// JiffyDOS protocol support for IEC - optimized load loop
|
||||
//
|
||||
|
||||
#if CONFIG_IEC_JIFFYDOS && !CONFIG_MEMORY_MODEL_60K
|
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|
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|
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// Note: original JiffyDOS LOAD loop checks for RUN/STOP key every time a sector is read,
|
||||
// see description at https://sites.google.com/site/h2obsession/CBM/C128/JiffySoft128
|
||||
//
|
||||
// For simplicity and some space savings, our routine does not check the RUN/STOP key at all;
|
||||
// the protocol is fast enough (especially with modern flash mediums) that probably nobody
|
||||
// will want to terminate the loading.
|
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|
||||
|
||||
jiffydos_load:
|
||||
|
||||
// XXX implement JiffyDOS optimized LOAD protocol, this one is ineffective
|
||||
|
||||
|
||||
// Timing is critical, do not allow interrupts
|
||||
sei
|
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|
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#if CONFIG_IEC_JIFFYDOS_BLANK
|
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|
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// Preserve register with screen status (blank/visible)
|
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lda VIC_SCROLY
|
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sta TBTCNT
|
||||
|
||||
// Blank screen to make sure no sprite/badline will interrupt
|
||||
jsr screen_off
|
||||
|
||||
// Preserve 3 lowest bits of CIA2_PRA XXX deduplicate this
|
||||
|
||||
lda CIA2_PRA
|
||||
and #%00000111
|
||||
sta C3PO
|
||||
|
||||
#else
|
||||
|
||||
// Store previous sprite status in temporary variable
|
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jsr jiffydos_prepare
|
||||
sta TBTCNT
|
||||
|
||||
#endif
|
||||
|
||||
// A trick to shorten EAL update time
|
||||
ldy #$FF
|
||||
|
||||
// FALLTROUGH
|
||||
|
||||
jiffydos_load_loop:
|
||||
|
||||
// Wait until device is ready to send (releases CLK)
|
||||
jsr iec_wait_for_clk_release
|
||||
|
||||
// Prepare 'start sending' message
|
||||
lda CIA2_PRA
|
||||
and #$FF - BIT_CIA2_PRA_DAT_OUT // release
|
||||
|
||||
#if CONFIG_IEC_JIFFYDOS_BLANK
|
||||
|
||||
// It seems JiffyDOS needs some time here; waste few cycles
|
||||
nop
|
||||
jsr iec_wait_rts
|
||||
|
||||
// Ask device to start sending bits
|
||||
sta CIA2_PRA
|
||||
|
||||
#else
|
||||
|
||||
// Wait for appropriate moment, ask device to start sending bits
|
||||
tax
|
||||
jsr jiffydos_wait_line
|
||||
stx CIA2_PRA // cycles: 4
|
||||
|
||||
#endif
|
||||
|
||||
// Prepare 'data pull' byte, cycles: 3 + 2 + 2 = 7
|
||||
lda C3PO
|
||||
ora #BIT_CIA2_PRA_DAT_OUT // pull
|
||||
tax
|
||||
|
||||
// Delay, JiffyDOS needs some time, 4 cycles
|
||||
nop
|
||||
nop
|
||||
|
||||
// Get bits, cycles: 4 + 2 + 2 = 8
|
||||
lda CIA2_PRA // bits 0 and 1 on CLK/DATA
|
||||
lsr
|
||||
lsr
|
||||
|
||||
// Delay, JiffyDOS needs some time, 2 cycles
|
||||
nop
|
||||
|
||||
// Get bits, cycles: 4 + 2 + 2 = 8
|
||||
ora CIA2_PRA // bits 2 and 3 on CLK/DATA
|
||||
lsr
|
||||
lsr
|
||||
|
||||
// Get bits, cycles: 3 + 4 + 2 + 2 = 11
|
||||
eor C3PO
|
||||
eor CIA2_PRA // bits 4 and 5 on CLK/DATA
|
||||
lsr
|
||||
lsr
|
||||
|
||||
// Get bits, cycles: 3 + 4 = 7
|
||||
eor C3PO
|
||||
eor CIA2_PRA // bits 6 and 7 on CLK/DATA
|
||||
|
||||
// Store retrieved byte, cycles: 2 + 6 = 8
|
||||
iny // NTSC needs this delay
|
||||
sta (EAL),y // not compatible with CONFIG_MEMORY_MODEL_60K
|
||||
|
||||
// Retrieve status bits, cycles: 4
|
||||
bit CIA2_PRA
|
||||
|
||||
// Pull DATA at the end, cycles: 4
|
||||
stx CIA2_PRA
|
||||
|
||||
// If CLK line not active - this was the last byte
|
||||
bvs jiffydos_load_end
|
||||
|
||||
// Handle EAL
|
||||
cpy #$FF
|
||||
bne jiffydos_load_loop
|
||||
inc EAL+1
|
||||
jmp jiffydos_load_loop
|
||||
|
||||
jiffydos_load_end:
|
||||
|
||||
// Save last byte
|
||||
tax
|
||||
|
||||
// Update EAL
|
||||
sec
|
||||
jsr iec_update_EAL_by_Y
|
||||
|
||||
// Indicate that no byte waits in output buffer
|
||||
lda #$00
|
||||
sta C3PO
|
||||
|
||||
// Restore proper IECPROTO value
|
||||
lda #$01
|
||||
sta IECPROTO
|
||||
|
||||
#if CONFIG_IEC_JIFFYDOS_BLANK
|
||||
|
||||
// Restore screen state
|
||||
lda TBTCNT
|
||||
sta VIC_SCROLY
|
||||
|
||||
#else
|
||||
|
||||
// Re-enable sprites
|
||||
lda TBTCNT
|
||||
sta VIC_SPENA
|
||||
|
||||
#endif
|
||||
|
||||
// Store last byte as unoptimized LOAD routine would
|
||||
stx TBTCNT
|
||||
|
||||
// No need to re-enable interrupts; other IEC routines
|
||||
// called by LOAD will do this nevertheless
|
||||
|
||||
// End of load loop
|
||||
jmp load_iec_loop_end
|
||||
|
||||
|
||||
#endif // CONFIG_IEC_JIFFYDOS and not CONFIG_MEMORY_MODEL_60K
|
||||
@@ -0,0 +1,32 @@
|
||||
// #LAYOUT# STD * #TAKE
|
||||
// #LAYOUT# * KERNAL_0 #TAKE
|
||||
// #LAYOUT# * * #IGNORE
|
||||
|
||||
//
|
||||
// JiffyDOS transfer preparation routine
|
||||
//
|
||||
|
||||
|
||||
#if CONFIG_IEC_JIFFYDOS
|
||||
|
||||
|
||||
jiffydos_prepare:
|
||||
|
||||
// We need to preserve 3 lowest bits of CIA2_PRA, they contain important
|
||||
// data - fortunately, the bits are never changed by external devices
|
||||
// Use C3PO for this, as afterwards we have to set there 0 nevertheless
|
||||
lda CIA2_PRA
|
||||
and #%00000111
|
||||
sta C3PO
|
||||
|
||||
// Hide sprites; JiffyDOS timing regime is very strict, before transmitting
|
||||
// anything we need to make sure nothing will steal the cycles
|
||||
|
||||
lda VIC_SPENA
|
||||
ldx #$00
|
||||
stx VIC_SPENA
|
||||
|
||||
rts
|
||||
|
||||
|
||||
#endif // CONFIG_IEC_JIFFYDOS
|
||||
@@ -0,0 +1,121 @@
|
||||
// #LAYOUT# STD * #TAKE
|
||||
// #LAYOUT# * KERNAL_0 #TAKE
|
||||
// #LAYOUT# * * #IGNORE
|
||||
|
||||
//
|
||||
// JiffyDOS protocol support for IEC - byte reception
|
||||
//
|
||||
|
||||
|
||||
#if CONFIG_IEC_JIFFYDOS
|
||||
|
||||
|
||||
jiffydos_rx_byte:
|
||||
|
||||
// Timing is critical, do not allow interrupts
|
||||
sei
|
||||
|
||||
// Store .X and .Y on the stack - preserve them
|
||||
phx_trash_a
|
||||
phy_trash_a
|
||||
|
||||
// Store previous sprite status on stack
|
||||
jsr jiffydos_prepare
|
||||
pha
|
||||
|
||||
// Wait until device is ready to send (releases CLK)
|
||||
jsr iec_wait_for_clk_release
|
||||
|
||||
// Prepare 'start sending' message
|
||||
lda CIA2_PRA
|
||||
and #$FF - BIT_CIA2_PRA_DAT_OUT // release
|
||||
tax
|
||||
|
||||
// Wait for appropriate moment
|
||||
jsr jiffydos_wait_line
|
||||
|
||||
// Ask device to start sending bits
|
||||
stx CIA2_PRA // cycles: 4
|
||||
|
||||
// Prepare 'data pull' byte, cycles: 3 + 2 + 2 = 7
|
||||
lda C3PO
|
||||
ora #BIT_CIA2_PRA_DAT_OUT // pull
|
||||
tax
|
||||
|
||||
// Delay, JiffyDOS needs some time, 4 cycles
|
||||
nop
|
||||
nop
|
||||
|
||||
// Get bits, cycles: 4 + 2 + 2 = 8
|
||||
lda CIA2_PRA // bits 0 and 1 on CLK/DATA
|
||||
lsr
|
||||
lsr
|
||||
|
||||
// Wait for the drive, cycles: 2
|
||||
nop
|
||||
|
||||
// Get bits, cycles: 4 + 2 + 2 = 8
|
||||
ora CIA2_PRA // bits 2 and 3 on CLK/DATA
|
||||
lsr
|
||||
lsr
|
||||
|
||||
// Get bits, cycles: 3 + 4 + 2 + 2 = 11
|
||||
eor C3PO
|
||||
eor CIA2_PRA // bits 4 and 5 on CLK/DATA
|
||||
lsr
|
||||
lsr
|
||||
|
||||
// Get bits, cycles: 3 + 4 = 7
|
||||
eor C3PO
|
||||
eor CIA2_PRA // bits 6 and 7 on CLK/DATA
|
||||
|
||||
// Preserve read byte, cycles: 3
|
||||
sta TBTCNT // $A4 is a byte buffer according to http://sta.c64.org/cbm64mem.html
|
||||
|
||||
// Delay, JiffyDOS needs some time; for PAL one NOP would be enough,
|
||||
// but NTSC machines are clocked slightly faster; cycles: 4
|
||||
nop
|
||||
nop
|
||||
|
||||
// Retrieve status bits, cycles: 4
|
||||
bit CIA2_PRA
|
||||
|
||||
// Pull DATA at the end, cycles: 4
|
||||
stx CIA2_PRA
|
||||
|
||||
// If CLK line active - success
|
||||
bvc jiffydos_rx_byte_end
|
||||
|
||||
// EOI or error, released DATA (highest byte set to 1) means error - see protocol analysis by Michael Steil, step R7a
|
||||
lda CIA2_PRA
|
||||
bmi jiffydos_rx_byte_error
|
||||
|
||||
// EOI - no error
|
||||
jsr kernalstatus_EOI
|
||||
|
||||
// FALLTROUGH
|
||||
|
||||
jiffydos_rx_byte_end:
|
||||
|
||||
// Indicate that no byte waits in output buffer
|
||||
lda #$00
|
||||
sta C3PO
|
||||
|
||||
// Restore proper IECPROTO value
|
||||
lda #$01
|
||||
sta IECPROTO
|
||||
|
||||
// Re-enable sprites
|
||||
pla
|
||||
sta VIC_SPENA
|
||||
|
||||
// End byte reception
|
||||
jmp iec_rx_end
|
||||
|
||||
jiffydos_rx_byte_error:
|
||||
|
||||
jsr kernalerror_IEC_TIMEOUT_READ
|
||||
bcs jiffydos_rx_byte_end // branch always
|
||||
|
||||
|
||||
#endif // CONFIG_IEC_JIFFYDOS
|
||||
@@ -0,0 +1,111 @@
|
||||
// #LAYOUT# STD * #TAKE
|
||||
// #LAYOUT# * KERNAL_0 #TAKE
|
||||
// #LAYOUT# * * #IGNORE
|
||||
|
||||
//
|
||||
// JiffyDOS protocol support for IEC - byte transfer
|
||||
//
|
||||
|
||||
|
||||
#if CONFIG_IEC_JIFFYDOS
|
||||
|
||||
|
||||
jiffydos_tx_byte:
|
||||
|
||||
// Timing is critical, do not allow interrupts
|
||||
sei
|
||||
|
||||
// If EOI requested (carry flag set), mark this in IECPROTO as 0
|
||||
bcc !+
|
||||
dec IECPROTO // turns 1 into 0
|
||||
!:
|
||||
// Store .X and .Y on the stack - preserve them
|
||||
phx_trash_a
|
||||
phy_trash_a
|
||||
|
||||
// Make sure we are not sending data on ATN
|
||||
jsr iec_release_atn
|
||||
|
||||
// Store previous sprite status on stack
|
||||
jsr jiffydos_prepare
|
||||
pha
|
||||
|
||||
// Prepare nibbles to send
|
||||
lda TBTCNT
|
||||
and #$0F
|
||||
tax
|
||||
lda jiffydos_bittable, X // low nibble has to be encoded
|
||||
pha
|
||||
lda TBTCNT
|
||||
and #$F0
|
||||
pha
|
||||
|
||||
// Prepare value for device notification
|
||||
ldx C3PO
|
||||
|
||||
// Wait till receiver is ready
|
||||
jsr iec_wait_for_data_release
|
||||
|
||||
// Wait till it is safe to send data
|
||||
jsr jiffydos_wait_line
|
||||
|
||||
// Notify device that we are going to send byte by releasing everything
|
||||
stx CIA2_PRA // cycles: 4
|
||||
// Send high nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 3 + 4 = 24
|
||||
pla // retrieve high nibble from stack
|
||||
ora C3PO // restore VIC-II and RS-232 bits
|
||||
sta CIA2_PRA // bits 4 and 5 on CLK/DATA
|
||||
lsr // move bits 6 and 7 to positions 4 and 5
|
||||
lsr
|
||||
and #%00110000 // clear everything but CLK/DATA
|
||||
ora C3PO
|
||||
sta CIA2_PRA // bits 6 and 7 on CLK/DATA
|
||||
|
||||
// Send low nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 4 = 21
|
||||
pla // retrieve low nibble from stack
|
||||
ora C3PO // restore VIC-II and RS-232 bits
|
||||
sta CIA2_PRA
|
||||
lsr
|
||||
lsr
|
||||
and #%00110000 // clear everything but CLK/DATA
|
||||
sta CIA2_PRA
|
||||
|
||||
// Signal EOI if needed; cycles till no EOI: 3 + 3 + 2 + 2 + 4 = 14
|
||||
lda C3PO
|
||||
ldx IECPROTO
|
||||
beq jiffydos_tx_byte_wait_eoi
|
||||
|
||||
// FALLTROUGH
|
||||
|
||||
jiffydos_tx_byte_finalize:
|
||||
|
||||
ora #BIT_CIA2_PRA_CLK_OUT // pull CLK
|
||||
sta CIA2_PRA
|
||||
|
||||
// Restore proper IECPROTO value
|
||||
lda #$01
|
||||
sta IECPROTO
|
||||
|
||||
// Re-enable sprites and interrupts
|
||||
pla
|
||||
sta VIC_SPENA
|
||||
cli
|
||||
|
||||
// Return success
|
||||
jmp iec_return_success
|
||||
|
||||
|
||||
jiffydos_tx_byte_wait_eoi:
|
||||
|
||||
sta CIA2_PRA
|
||||
jsr iec_wait20us
|
||||
lda C3PO
|
||||
|
||||
// According to protocol analysis by Michael Steil (step S8) we should pull the DATA here
|
||||
// to signal there was no error; but DATA pulled by the controller is a normal state
|
||||
// (which should be stored in C3PO), so there is nothing to do here.
|
||||
|
||||
jmp jiffydos_tx_byte_finalize
|
||||
|
||||
|
||||
#endif // CONFIG_IEC_JIFFYDOS
|
||||
@@ -0,0 +1,37 @@
|
||||
// #LAYOUT# STD * #TAKE
|
||||
// #LAYOUT# * KERNAL_0 #TAKE
|
||||
// #LAYOUT# * * #IGNORE
|
||||
|
||||
//
|
||||
// JiffyDOS helper routine to wait for appropriate moment,
|
||||
// where no badline will interrupt the transmission
|
||||
//
|
||||
|
||||
|
||||
#if CONFIG_IEC_JIFFYDOS
|
||||
|
||||
|
||||
jiffydos_wait_line:
|
||||
|
||||
// One might try to optimize the code by checking for disabled screen
|
||||
// (bit 4 of VIC_SCROLY); problem: VIC checks this bit only once per frame:
|
||||
// - https://www.lemon64.com/forum/viewtopic.php?t=56582
|
||||
// so it would complicated the code
|
||||
|
||||
// Avoid 2 lines before the badline, otherwise VIC will ruin the synchronization
|
||||
lda VIC_RASTER
|
||||
cmp #$2E
|
||||
bcc jiffydos_wait_line_done // we are safe, border - lot of time till badline
|
||||
!:
|
||||
lda VIC_RASTER // carry+ is definitely set here!
|
||||
sbc VIC_SCROLY
|
||||
and #$07 // we want 8 lowest bits
|
||||
cmp #$06
|
||||
bcs !-
|
||||
|
||||
jiffydos_wait_line_done:
|
||||
|
||||
rts
|
||||
|
||||
|
||||
#endif // CONFIG_IEC_JIFFYDOS
|
||||
Reference in new issue
Block a user