set IRQ frequency depending on video system

c64/kernal/fda3.ioinit.s

@@ -34,35 +34,54 @@ ioinit:
 	cpy #$80 ; $20 * amount of chips to silence, $80 to silence 4 chips
 	bne -
 
-	;; Enable CIA1 IRQ and ~50Hz timer
-	;; (https://csdb.dk/forums/?roomid=11&topicid=69037)
-	lda #$7f
-	sta $DC0D 		; First disable all
+	;; XXX: calibrate TOD for both CIA's, see here: https://codebase64.org/doku.php?id=base:efficient_tod_initialisation
+
+	;; Enable CIA1 IRQ and ~50Hz timer (https://csdb.dk/forums/?roomid=11&topicid=69037)
+	lda #$7F
+	sta CIA1_ICR ; disable all
 
 	;; Set timer interval to ~1/60th of a second
-	;; (This value was calculated by running a custom IRQ haandler on a C64
+	jsr setup_pal_ntsc
+	
+	;; (This value was calculated by running a custom IRQ handler on a C64
 	;; with original KERNAL, and writing the values of $DC04/5 to the screen
 	;; in the IRQ handler to see roughly what value the timers must be set to)
-	lda #<16380
-	sta $dc04
-	lda #>16380
-	sta $dc05
+	;; ldy #<16380
+	;; ldx #>16380
+
+	;; PAL C64 (https://codebase64.org/doku.php?id=base:cpu_clocking),
+	;; is clocked at 0.985248 MHz, so that 1/60s is 16421 CPU cycles
+
+	ldy #<16421
+	ldx #>16421
+
+	lda PALNTSC
+	bne +
+
+	;; NTSC C64 (https://codebase64.org/doku.php?id=base:cpu_clocking),
+	;; is clocked at 1.022727 MHz, so that 1/60s is 17045 CPU cycles
+
+	ldy #<17045
+	ldx #>17045
+
+	;; Store the IRQ timing constant to CIA chip
+*
+	sty CIA1_TIMALO
+	stx CIA1_TIMAHI
 
 	;; Enable timer interrupt
 	lda #$81
-	sta $dc0d
+	sta CIA1_ICR
 
-	;; Enable timer A to run continuously
-	;; (http://codebase64.org/doku.php?id=base:timerinterrupts)
+	;; Enable timer A to run continuously (http://codebase64.org/doku.php?id=base:timerinterrupts)
 	lda #$11
-	sta $dc0e
-	lda $dc0d
+	sta CIA1_CRA
+	lda CIA1_ICR
 
 	;; Set DDR on CIA2 for IEC bus, VIC-II banking
-	lda #$3b
-	sta $dd02
-	
-	;; Set IEC bus oto its initial idle state
-	jsr iec_set_idle
-	
-	rts
+	lda #$3B
+	sta CIA2_DDRA
+
+	;; Set IEC bus to its initial idle state
+	jmp iec_set_idle
+