From 7fe0e062ace64c87fcc14129e8fd3b5b6be6668d Mon Sep 17 00:00:00 2001
From: FeralChild64 <you@example.com>
Date: Sun, 17 Jan 2021 11:54:03 +0100
Subject: [PATCH] more work on register setting

---
 src/mon_m65/,aliases_mon.s             | 16 +++++-----
 src/mon_m65/bsmon.s                    | 20 ++++++------
 src/mon_m65/mon_command_set_register.s | 44 ++++++++++++++++++++++++--
 3 files changed, 60 insertions(+), 20 deletions(-)

diff --git a/src/mon_m65/,aliases_mon.s b/src/mon_m65/,aliases_mon.s
index d54a3fba..280cd665 100644
--- a/src/mon_m65/,aliases_mon.s
+++ b/src/mon_m65/,aliases_mon.s
@@ -13,14 +13,14 @@
 !addr Addr_Mode     =  2       ; $00 = 64K address, $80 = M65 flat address
 !addr PCH           =  3
 !addr PCL           =  4
-!addr SR            =  5
-!addr AC            =  6
-!addr XR            =  7
-!addr YR            =  8
-!addr ZR            =  9
-!addr BP            = 10
-!addr SPH           = 11
-!addr SPL           = 12
+!addr AC            =  5
+!addr XR            =  6
+!addr YR            =  7
+!addr ZR            =  8
+!addr BP            =  9
+!addr SPH           = 10
+!addr SPL           = 11
+!addr SR            = 12
 
 ; *******************
 ; * Other variables *
diff --git a/src/mon_m65/bsmon.s b/src/mon_m65/bsmon.s
index 45264b23..4b41faa2 100644
--- a/src/mon_m65/bsmon.s
+++ b/src/mon_m65/bsmon.s
@@ -63,13 +63,13 @@ Mon_Register:
          LDA  PCH
          JSR  Print_Hex
 
-; print PCL,SR,PCL,A,X,Y,Z,BP
+; print PCL,A,X,Y,Z,BP
 
          LDY  #0
 @loopb   LDA  PCL,Y
          JSR  Print_Hex_Blank
          INY
-         CPY  #7
+         CPY  #6
          BCC  @loopb
 
 ; print 16 bit stack pointer
@@ -126,6 +126,8 @@ Main_A:
 Mon_Switch:
 ; *********
 
+         CMP  #'?'
+         +beq Mon_Help
          LDX  #24
 @loop    CMP  Command_Char,X
          BEQ  Mon_Select
@@ -151,7 +153,7 @@ Mon_Select:
 ; *********
 
          STA  VERCKK
-         CPX  #22
+         CPX  #21
          LBCS Load_Save
          TXA
          ASL
@@ -163,14 +165,14 @@ Print_Commands:
 ; *************
 
          JSR  PRIMM
-         !pet KEY_RETURN," ",KEY_RVS_ON," commands: "
+         !pet KEY_RETURN,KEY_RVS_ON," commands: "
 
 ; ***********
 Command_Char:
 ; ***********
 
          ;     0123456789abcdef
-         !pet "abcdfghjmrtx@.>;?"
+         !pet "abcdfghjmrtx@.>;"
 
 ; **********
 Cons_Prefix:
@@ -182,7 +184,8 @@ Cons_Prefix:
 Load_Save_Verify:
 ; ***************
 
-         !pet "lsv ",KEY_RETURN,0
+         !pet "lsv ",KEY_RETURN
+         !pet KEY_RVS_ON," for help: type ? and press return ",KEY_RETURN,0
          RTS
 
 ; *********
@@ -204,8 +207,7 @@ Jump_Table:
          !word Mon_DOS          ; @
          !word Mon_Assemble     ; .  XXX to be debugged/adapted
          !word Mon_Set_Memory   ; >
-         !word Mon_Set_Register ; ;  XXX to be debugged/adapted
-         !word Mon_Help         ; ?
+         !word Mon_Set_Register ; ;  XXX to be bugfixed
          !word Converter        ; $
          !word Converter        ; +
          !word Converter        ; &
@@ -2150,7 +2152,7 @@ Reg_Text:
 ; *******
 
          JSR  PRIMM
-         !pet KEY_RETURN, "   pc  sr ac xr yr zr bp  sp  nvebdizc", KEY_RETURN, "; ", KEY_ESC, 'q', 0
+         !pet KEY_RETURN, "   pc  ac xr yr zr bp  sp  nvebdizc", KEY_RETURN, "; ", KEY_ESC, 'q', 0
          RTS
 
 ; *******
diff --git a/src/mon_m65/mon_command_set_register.s b/src/mon_m65/mon_command_set_register.s
index 160b37c6..836245fa 100644
--- a/src/mon_m65/mon_command_set_register.s
+++ b/src/mon_m65/mon_command_set_register.s
@@ -24,10 +24,10 @@ Mon_Set_Register:
 	jsr  Syntax_Byte_AC
 
 	lda  Long_AC+0
-	sta  SR,Y
+	sta  AC,Y
 
 	iny
-	cpy  #$06
+	cpy  #$05
 	bne  @lpreg
 
 	; SP - 16 bit
@@ -41,9 +41,47 @@ Mon_Set_Register:
 
 	; Flags
 
+	jsr  Get_Glyph
+	beq  @exit
+	dec  Buf_Index
 
+	lda  #%01111111          ; prepare helper values for bit set/clear
+	sta  Long_TMP+0
+	lda  #%10000000
+	sta  Long_TMP+1
 
-	; XXX
+@lpflag:
+
+	lda  Get_Char
+	beq  @exit
+
+	cmp  #'-'
+	beq  @bit_clr
+	cmp  #'1'
+	+bne Mon_Error
+
+@bit_set:
+
+	lda  SR
+	ora  Long_TMP+1
+
+	bra  @next
+
+@bit_clr:
+
+	lda  SR
+	and  Long_TMP+0
+
+@next:
+
+	sta  SR
+
+	sec
+	rol  Long_TMP+0
+	clc 
+	rol  Long_TMP+1
+
+	bne  @lpflag
 
 @exit: