don't corrupt Y register in iec_wait60ns
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@@ -1,9 +1,9 @@
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iec_wait60us:
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iec_wait60us:
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;; Waste ~60 clock cycles (including JSR + RTS)
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;; Waste ~60 clock cycles (including JSR + RTS)
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ldx #$06
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ldy #$06
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* lda $dd00
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* lda $dd00
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dex
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dey
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bpl -
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bpl -
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rts
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rts
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