From 8de19d4be0d5ca3d8e16ca40c4cd7426f5a4330f Mon Sep 17 00:00:00 2001 From: FeralChild64 Date: Sun, 20 Dec 2020 18:59:42 +0100 Subject: [PATCH] added illegal Z80 instruction opcodes --- src/zvm_m65/,aliases_zvm.s | 4 +++ src/zvm_m65/2000.zvm_vectable.s | 26 ++++++++-------- src/zvm_m65/z80_instr_bit.s | 14 +++++++++ src/zvm_m65/zvm_core.s | 53 ++++++++++++++++++++++++++++----- 4 files changed, 77 insertions(+), 20 deletions(-) diff --git a/src/zvm_m65/,aliases_zvm.s b/src/zvm_m65/,aliases_zvm.s index 483d5053..2e3eeeb0 100644 --- a/src/zvm_m65/,aliases_zvm.s +++ b/src/zvm_m65/,aliases_zvm.s @@ -37,6 +37,10 @@ !addr REG_IFF1 = $23 ; interrupt flip-flop flag 1 !addr REG_IFF2 = $24 ; interrupt flip-flop flag 2 +!addr REG_TMP1 = $25 ; emulation-specific temporary storage +!addr REG_TMP2 = $26 + + !addr VEC_fetch_value = $60 !addr VEC_fetch_stack = $62 !addr VEC_store_stack = $64 diff --git a/src/zvm_m65/2000.zvm_vectable.s b/src/zvm_m65/2000.zvm_vectable.s index b3abe91b..9ad98e99 100644 --- a/src/zvm_m65/2000.zvm_vectable.s +++ b/src/zvm_m65/2000.zvm_vectable.s @@ -74,7 +74,7 @@ Z80_vectab_CB_0: !word Z80_instr_CB_20, Z80_instr_CB_21, Z80_instr_CB_22, Z80_instr_CB_23, Z80_instr_CB_24, Z80_instr_CB_25, Z80_instr_CB_26, Z80_instr_CB_27 !word Z80_instr_CB_28, Z80_instr_CB_29, Z80_instr_CB_2A, Z80_instr_CB_2B, Z80_instr_CB_2C, Z80_instr_CB_2D, Z80_instr_CB_2E, Z80_instr_CB_2F - !word Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD, Z80_illegal__DD + !word Z80_illeg_CB_30, Z80_illeg_CB_31, Z80_illeg_CB_32, Z80_illeg_CB_33, Z80_illeg_CB_34, Z80_illeg_CB_35, Z80_illeg_CB_36, Z80_illeg_CB_37 !word Z80_instr_CB_38, Z80_instr_CB_39, Z80_instr_CB_3A, Z80_instr_CB_3B, Z80_instr_CB_3C, Z80_instr_CB_3D, Z80_instr_CB_3E, Z80_instr_CB_3F !word Z80_instr_CB_40, Z80_instr_CB_41, Z80_instr_CB_42, Z80_instr_CB_43, Z80_instr_CB_44, Z80_instr_CB_45, Z80_instr_CB_46, Z80_instr_CB_47 @@ -182,16 +182,16 @@ Z80_vectab_ED_0: !word Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED !word Z80_instr_ED_40, Z80_instr_ED_41, Z80_instr_ED_42, Z80_instr_ED_43, Z80_instr_ED_44, Z80_instr_ED_45, Z80_instr_ED_46, Z80_instr_ED_47 - !word Z80_instr_ED_48, Z80_instr_ED_49, Z80_instr_ED_4A, Z80_instr_ED_4B, Z80_illegal__ED, Z80_instr_ED_4D, Z80_illegal__ED, Z80_instr_ED_4F + !word Z80_instr_ED_48, Z80_instr_ED_49, Z80_instr_ED_4A, Z80_instr_ED_4B, Z80_illeg_ED_4C, Z80_instr_ED_4D, Z80_illeg_ED_4E, Z80_instr_ED_4F - !word Z80_instr_ED_50, Z80_instr_ED_51, Z80_instr_ED_52, Z80_instr_ED_53, Z80_illegal__ED, Z80_illegal__ED, Z80_instr_ED_56, Z80_instr_ED_57 - !word Z80_instr_ED_58, Z80_instr_ED_59, Z80_instr_ED_5A, Z80_instr_ED_5B, Z80_illegal__ED, Z80_illegal__ED, Z80_instr_ED_5E, Z80_instr_ED_5F + !word Z80_instr_ED_50, Z80_instr_ED_51, Z80_instr_ED_52, Z80_instr_ED_53, Z80_illeg_ED_54, Z80_illeg_ED_55, Z80_instr_ED_56, Z80_instr_ED_57 + !word Z80_instr_ED_58, Z80_instr_ED_59, Z80_instr_ED_5A, Z80_instr_ED_5B, Z80_illeg_ED_5C, Z80_illeg_ED_5D, Z80_instr_ED_5E, Z80_instr_ED_5F - !word Z80_instr_ED_60, Z80_instr_ED_61, Z80_instr_ED_62, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_instr_ED_67 - !word Z80_instr_ED_68, Z80_instr_ED_69, Z80_instr_ED_6A, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_instr_ED_6F + !word Z80_instr_ED_60, Z80_instr_ED_61, Z80_instr_ED_62, Z80_illegal__ED, Z80_illeg_ED_64, Z80_illeg_ED_65, Z80_illeg_ED_66, Z80_instr_ED_67 + !word Z80_instr_ED_68, Z80_instr_ED_69, Z80_instr_ED_6A, Z80_illegal__ED, Z80_illeg_ED_6C, Z80_illeg_ED_6D, Z80_illeg_ED_6E, Z80_instr_ED_6F - !word Z80_illegal__ED, Z80_illegal__ED, Z80_instr_ED_72, Z80_instr_ED_73, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED - !word Z80_instr_ED_78, Z80_instr_ED_79, Z80_instr_ED_7A, Z80_instr_ED_7B, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED, Z80_illegal__ED + !word Z80_illeg_ED_70, Z80_illeg_ED_71, Z80_instr_ED_72, Z80_instr_ED_73, Z80_illeg_ED_74, Z80_illeg_ED_75, Z80_illeg_ED_76, Z80_illeg_ED_77 + !word Z80_instr_ED_78, Z80_instr_ED_79, Z80_instr_ED_7A, Z80_instr_ED_7B, Z80_illeg_ED_7C, Z80_illeg_ED_7D, Z80_illeg_ED_7E, Z80_illeg_ED_7F Z80_vectab_ED_1: @@ -295,12 +295,12 @@ Z80_vectab_DDCB_0: !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_6E, Z80_illegal__DDCB !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_76, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_6E, Z80_illegal__DDCB + !word Z80_illeg_DDCB_78, Z80_illeg_DDCB_79, Z80_illeg_DDCB_7A, Z80_illeg_DDCB_7B, Z80_illeg_DDCB_7C, Z80_illeg_DDCB_7D, Z80_instr_DDCB_7E, Z80_illeg_DDCB_7F Z80_vectab_DDCB_1: !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_86, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_7E, Z80_illegal__DDCB + !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_8E, Z80_illegal__DDCB !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_96, Z80_illegal__DDCB !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_9E, Z80_illegal__DDCB @@ -311,7 +311,7 @@ Z80_vectab_DDCB_1: !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_B6, Z80_illegal__DDCB !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_BE, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_C6, Z80_illegal__DDCB + !word Z80_illeg_DDCB_C0, Z80_illeg_DDCB_C1, Z80_illeg_DDCB_C2, Z80_illeg_DDCB_C3, Z80_illeg_DDCB_C4, Z80_illeg_DDCB_C5, Z80_instr_DDCB_C6, Z80_illeg_DDCB_C7 !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_CE, Z80_illegal__DDCB !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_D6, Z80_illegal__DDCB @@ -347,7 +347,7 @@ Z80_vectab_FDCB_0: !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_6E, Z80_illegal__FDCB !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_76, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_7E, Z80_illegal__FDCB + !word Z80_illeg_FDCB_78, Z80_illeg_FDCB_79, Z80_illeg_FDCB_7A, Z80_illeg_FDCB_7B, Z80_illeg_FDCB_7C, Z80_illeg_FDCB_7D, Z80_instr_FDCB_7E, Z80_illeg_FDCB_7F Z80_vectab_FDCB_1: @@ -363,7 +363,7 @@ Z80_vectab_FDCB_1: !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_B6, Z80_illegal__FDCB !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_BE, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_C6, Z80_illegal__FDCB + !word Z80_illeg_FDCB_C0, Z80_illeg_FDCB_C1, Z80_illeg_FDCB_C2, Z80_illeg_FDCB_C3, Z80_illeg_FDCB_C4, Z80_illeg_FDCB_C5, Z80_instr_FDCB_C6, Z80_illeg_FDCB_C7 !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_CE, Z80_illegal__FDCB !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_D6, Z80_illegal__FDCB diff --git a/src/zvm_m65/z80_instr_bit.s b/src/zvm_m65/z80_instr_bit.s index 0ec05417..8b086c9d 100644 --- a/src/zvm_m65/z80_instr_bit.s +++ b/src/zvm_m65/z80_instr_bit.s @@ -489,7 +489,14 @@ Z80_instr_DDCB_76: ; BIT 6,(IX+d) bne Z80_common_bitXYx_1 bra Z80_common_bitXYx_0 +Z80_illeg_DDCB_78: ; BIT 7,(IX+d) +Z80_illeg_DDCB_79: ; BIT 7,(IX+d) +Z80_illeg_DDCB_7A: ; BIT 7,(IX+d) +Z80_illeg_DDCB_7B: ; BIT 7,(IX+d) +Z80_illeg_DDCB_7C: ; BIT 7,(IX+d) +Z80_illeg_DDCB_7D: ; BIT 7,(IX+d) Z80_instr_DDCB_7E: ; BIT 7,(IX+d) +Z80_illeg_DDCB_7F: ; BIT 7,(IX+d) jsr (VEC_fetch_via_IX_d) and #%10000000 @@ -582,7 +589,14 @@ Z80_instr_FDCB_76: ; BIT 6,(IY+d) bne Z80_common_bitXYx_1 bra Z80_common_bitXYx_0 +Z80_illeg_FDCB_78: ; BIT 7,(IY+d) +Z80_illeg_FDCB_79: ; BIT 7,(IY+d) +Z80_illeg_FDCB_7A: ; BIT 7,(IY+d) +Z80_illeg_FDCB_7B: ; BIT 7,(IY+d) +Z80_illeg_FDCB_7C: ; BIT 7,(IY+d) +Z80_illeg_FDCB_7D: ; BIT 7,(IY+d) Z80_instr_FDCB_7E: ; BIT 7,(IY+d) +Z80_illeg_FDCB_7F: ; BIT 7,(IY+d) jsr (VEC_fetch_via_IY_d) and #%10000000 diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s index 06d6d912..c0746e1d 100644 --- a/src/zvm_m65/zvm_core.s +++ b/src/zvm_m65/zvm_core.s @@ -62,10 +62,17 @@ Z80_instr_6D: ; Z80_instr_7F: ; LD A,A ; For interrupts (not emulated as of yet) Z80_instr_ED_46: ; IM 0 +Z80_illeg_ED_4E: ; IM 0 +Z80_illeg_ED_66: ; IM 0 +Z80_illeg_ED_6E: ; IM 0 Z80_instr_ED_56: ; IM 1 +Z80_illeg_ED_76: ; IM 1 Z80_instr_ED_5E: ; IM 2 +Z80_illeg_ED_7E: ; IM 2 ; Real NOP Z80_instr_00: ; NOP +Z80_illeg_ED_77: ; NOP +Z80_illeg_ED_7F: ; NOP ; Dispatch via jumptable ZVM_next: +ZVM_DISPATCH Z80_vectab_0, Z80_vectab_1 Z80_instr_CB: +ZVM_DISPATCH Z80_vectab_CB_0, Z80_vectab_CB_1 ; #CB @@ -86,12 +93,6 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ; - - - - - - ; ; Not implemented yet - XXX implement them! @@ -371,7 +372,45 @@ Z80_instr_FDCB_1E: ; RR (IY+d) Z80_instr_FDCB_26: ; SLA (IY+d) Z80_instr_FDCB_2E: ; SRA (IY+d) Z80_instr_FDCB_3E: ; SRL (IY+d) +Z80_illeg_CB_30: ; SLL B +Z80_illeg_CB_31: ; SLL C +Z80_illeg_CB_32: ; SLL D +Z80_illeg_CB_33: ; SLL E +Z80_illeg_CB_34: ; SLL H +Z80_illeg_CB_35: ; SLL L +Z80_illeg_CB_36: ; SLL (HL) +Z80_illeg_CB_37: ; SLL A +Z80_illeg_ED_4C: ; NEG +Z80_illeg_ED_54: ; NEG +Z80_illeg_ED_55: ; RETN +Z80_illeg_ED_5C: ; NEG +Z80_illeg_ED_5D: ; RETN +Z80_illeg_ED_64: ; NEG +Z80_illeg_ED_65: ; RETN +Z80_illeg_ED_6C: ; NEG +Z80_illeg_ED_6D: ; RETN +Z80_illeg_ED_70: ; IN F,(C) +Z80_illeg_ED_71: ; OUT (C),0 +Z80_illeg_ED_74: ; NEG +Z80_illeg_ED_75: ; RETN +Z80_illeg_ED_7C: ; NEG +Z80_illeg_ED_7D: ; RETN +Z80_illeg_DDCB_C0: ; SET 0,(IX+d),B +Z80_illeg_DDCB_C1: ; SET 0,(IX+d),C +Z80_illeg_DDCB_C2: ; SET 0,(IX+d),D +Z80_illeg_DDCB_C3: ; SET 0,(IX+d),E +Z80_illeg_DDCB_C4: ; SET 0,(IX+d),H +Z80_illeg_DDCB_C5: ; SET 0,(IX+d),L +Z80_illeg_DDCB_C7: ; SET 0,(IX+d),A +Z80_illeg_FDCB_C0: ; SET 0,(IY+d),B +Z80_illeg_FDCB_C1: ; SET 0,(IY+d),C +Z80_illeg_FDCB_C2: ; SET 0,(IY+d),D +Z80_illeg_FDCB_C3: ; SET 0,(IY+d),E +Z80_illeg_FDCB_C4: ; SET 0,(IY+d),H +Z80_illeg_FDCB_C5: ; SET 0,(IY+d),L +Z80_illeg_FDCB_C7: ; SET 0,(IY+d),A jmp ZVM_next ; XXX - ; XXX add 'illegal' instructions + + ; XXX add illegal instructions for combination of prefixes