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fix potential IEC data transfer problem

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FeralChild64 committed 2019-08-25 13:25:03 +02:00
1 parent b954d23a6b
commit 8eb435d2b2
2 files changed
+11 -3
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c64/kernal/iec/iec_pull_clk_release_data_oneshot.s
+8
View File
@@ -0,0 +1,8 @@
iec_pull_clk_release_data_oneshot:
lda CIA2_PRA
ora #BIT_CIA2_PRA_CLK_OUT ; pull
and #$FF - BIT_CIA2_PRA_DAT_OUT ; release
sta CIA2_PRA
rts
c64/kernal/iec/iec_tx_common.s
+3 -3
View File
@@ -33,7 +33,7 @@ iec_tx_common:
;; Pull CLK back to indicate that DATA is not valid, keep it for 60us ;; Pull CLK back to indicate that DATA is not valid, keep it for 60us
;; We can use this routine as we don't hold DATA anyway (and its state doesn't even matter) ;; We can use this routine as we don't hold DATA anyway (and its state doesn't even matter)
jsr iec_pull_clk_release_data jsr iec_pull_clk_release_data_oneshot
jsr iec_wait60us jsr iec_wait60us
;; Now, we can start transmission of 8 bits of data ;; Now, we can start transmission of 8 bits of data
@@ -60,8 +60,8 @@ iec_tx_common_bit_is_sent:
;; Pull CLK for 20us again, before sending the next bit ;; Pull CLK for 20us again, before sending the next bit
;; or performing any other action ;; or performing any other action
jsr iec_pull_clk_release_data jsr iec_pull_clk_release_data_oneshot
jsr iec_wait20us ; XXX this might be an overkill, there is a lot of code besides this wait here - few NOPs might be enough jsr iec_wait20us
;; More bits to send? ;; More bits to send?
dex dex