From 9410ab9aed6de79aa1edd1e0d11c8c970fe06051 Mon Sep 17 00:00:00 2001 From: FeralChild64 Date: Sat, 19 Dec 2020 23:44:44 +0100 Subject: [PATCH] small Z80 additions --- src/zvm_m65/,aliases_zvm.s | 44 +++++++++++++++------ src/zvm_m65/z80_instr_rotate_shift.s | 57 ++++++++++++++++++++++++++++ src/zvm_m65/zvm_banking.s | 10 ----- src/zvm_m65/zvm_core.s | 15 ++------ 4 files changed, 92 insertions(+), 34 deletions(-) diff --git a/src/zvm_m65/,aliases_zvm.s b/src/zvm_m65/,aliases_zvm.s index b7cd7ec5..f75fbbe7 100644 --- a/src/zvm_m65/,aliases_zvm.s +++ b/src/zvm_m65/,aliases_zvm.s @@ -33,18 +33,17 @@ !addr REG_IFF1 = $1F ; interrupt flip-flop flag 1 !addr REG_IFF2 = $20 ; interrupt flip-flop flag 2 -!addr VEC_fetch_opcode = $60 -!addr VEC_fetch_value = $62 -!addr VEC_fetch_stack = $64 -!addr VEC_store_stack = $66 -!addr VEC_fetch_via_HL = $68 -!addr VEC_store_via_HL = $6A -!addr VEC_fetch_via_IX_d = $6C -!addr VEC_fetch_via_IY_d = $6E -!addr VEC_store_via_IX_d = $70 -!addr VEC_store_via_IY_d = $72 -!addr VEC_fetch_via_nn = $74 -!addr VEC_store_via_nn = $76 +!addr VEC_fetch_value = $60 +!addr VEC_fetch_stack = $62 +!addr VEC_store_stack = $64 +!addr VEC_fetch_via_HL = $66 +!addr VEC_store_via_HL = $68 +!addr VEC_fetch_via_IX_d = $6A +!addr VEC_fetch_via_IY_d = $6C +!addr VEC_store_via_IX_d = $6E +!addr VEC_store_via_IY_d = $70 +!addr VEC_fetch_via_nn = $72 +!addr VEC_store_via_nn = $74 ; Masks for Z80 flag (F) register @@ -57,3 +56,24 @@ !set Z80_VF = %00000100 ; overflow !set Z80_NF = %00000010 ; subtract !set Z80_CF = %00000001 ; carry + +; Macros to set/reset flags - to avoid mistakes + +!macro Z80_PUT_1_SF { smb7 REG_F } +!macro Z80_PUT_0_SF { rmb7 REG_F } +!macro Z80_PUT_1_ZF { smb6 REG_F } +!macro Z80_PUT_0_ZF { rmb6 REG_F } +!macro Z80_PUT_1_YF { smb5 REG_F } +!macro Z80_PUT_0_YF { rmb5 REG_F } +!macro Z80_PUT_1_HF { smb4 REG_F } +!macro Z80_PUT_0_HF { rmb4 REG_F } +!macro Z80_PUT_1_XF { smb3 REG_F } +!macro Z80_PUT_0_XF { rmb3 REG_F } +!macro Z80_PUT_1_PF { smb2 REG_F } +!macro Z80_PUT_0_PF { rmb2 REG_F } +!macro Z80_PUT_1_VF { smb2 REG_F } +!macro Z80_PUT_0_VF { rmb2 REG_F } +!macro Z80_PUT_1_NF { smb1 REG_F } +!macro Z80_PUT_0_NF { rmb1 REG_F } +!macro Z80_PUT_1_CF { smb0 REG_F } +!macro Z80_PUT_0_CF { rmb0 REG_F } diff --git a/src/zvm_m65/z80_instr_rotate_shift.s b/src/zvm_m65/z80_instr_rotate_shift.s index c46b5e13..8db3c5af 100644 --- a/src/zvm_m65/z80_instr_rotate_shift.s +++ b/src/zvm_m65/z80_instr_rotate_shift.s @@ -2,3 +2,60 @@ ; ; Z80 rotate/shift instructions ; + + +Z80_instr_07: ; RLCA + + lda REG_F + and #($FF - Z80_HF - Z80_NF - Z80_CF) + sta REG_F + + asl REG_A + +bcc ZVM_next + inc REG_A + +Z80_PUT_1_CF + jmp ZVM_next + +Z80_instr_17: ; RLA + + lda REG_F + and #($FF - Z80_HF - Z80_NF - Z80_CF) + sta REG_F + + clc + bbr0 REG_F, @1 + sec +@1: + rol REG_A + +bcc ZVM_next + +Z80_PUT_1_CF + jmp ZVM_next + +Z80_instr_0F: ; RRCA + + lda REG_F + and #($FF - Z80_HF - Z80_NF - Z80_CF) + sta REG_F + + clc + ror REG_A + +bcc ZVM_next + smb7 REG_A + +Z80_PUT_1_CF + jmp ZVM_next + +Z80_instr_1F: ; RRA + + lda REG_F + and #($FF - Z80_HF - Z80_NF - Z80_CF) + sta REG_F + + clc + bbr0 REG_F, @1 + sec +@1: + ror REG_A + +bcc ZVM_next + +Z80_PUT_1_CF + jmp ZVM_next + diff --git a/src/zvm_m65/zvm_banking.s b/src/zvm_m65/zvm_banking.s index 9b365191..fe7dcf3d 100644 --- a/src/zvm_m65/zvm_banking.s +++ b/src/zvm_m65/zvm_banking.s @@ -8,11 +8,6 @@ ZVM_set_bank_0: ; XXX consider switchink banks using DMA list - lda #ZVM_fetch_opcode_bank_0 - sta VEC_fetch_opcode+1 - lda #ZVM_fetch_value_bank_0 @@ -72,11 +67,6 @@ ZVM_set_bank_0: ZVM_set_bank_1: - lda #ZVM_fetch_opcode_bank_1 - sta VEC_fetch_opcode+1 - lda #ZVM_fetch_value_bank_1 diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s index c9e50973..653133a6 100644 --- a/src/zvm_m65/zvm_core.s +++ b/src/zvm_m65/zvm_core.s @@ -39,7 +39,8 @@ ZVM_next: ; fetch and execute next opcode ; CPU main loop - jsr (VEC_fetch_opcode) + inc REG_R06 + jsr (VEC_fetch_value) asl bcs @1 @@ -86,12 +87,6 @@ ZVM_next: ; fetch and execute next opcode - - - - - - @@ -111,18 +106,14 @@ Z80_instr_DD_CB: ; #DDCB Z80_instr_FD_CB: ; #FDCB Z80_instr_01: ; LD BC,nn Z80_instr_02: ; LD (BC),A -Z80_instr_07: ; RLCA Z80_instr_09: ; ADD HL,BC Z80_instr_0A: ; LD A,(BC) -Z80_instr_0F: ; RRCA Z80_instr_10: ; DJNZ e Z80_instr_11: ; LD DE,nn Z80_instr_12: ; LD (DE),A -Z80_instr_17: ; RLA Z80_instr_18: ; JR e Z80_instr_19: ; ADD HL,DE -Z80_instr_1A: ; LD A,(DE) -Z80_instr_1F: ; RRA +Z80_instr_1A: ; LD A,(DE) Z80_instr_20: ; JR NZ,e Z80_instr_21: ; LD HL,nn Z80_instr_22: ; LD (nn),HL