From 9f05cc3e4c2256bc9289da9709be322fdec7b142 Mon Sep 17 00:00:00 2001 From: Paul Gardner-Stephen Date: Sat, 4 May 2019 11:52:14 +0930 Subject: [PATCH] instrument to debug loading. --- c64/kernal/iec_rx_byte.s | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/c64/kernal/iec_rx_byte.s b/c64/kernal/iec_rx_byte.s index ff28b5aa..a0d557b8 100644 --- a/c64/kernal/iec_rx_byte.s +++ b/c64/kernal/iec_rx_byte.s @@ -5,13 +5,19 @@ iec_rx_byte: + inc $062f + ;; First, we wait for the talker to release the CLK line. jsr iec_wait_for_clock_release + inc $0630 + ;; We then release the data line ;; (We can use this routine, since we weren't holding CLK, anyway) jsr iec_release_clk_and_data + inc $0631 + ;; Wait for talker to assert CLK. ;; If >200usec, then it is EOI and we have to assert the ;; DATA line for 60 usec to tell the TALKER that we have @@ -24,6 +30,8 @@ iec_rx_clk_wait: dex bpl iec_rx_clk_wait + inc $0632 + ;; EOI timeout: So pulse DATA line for 60 usec jsr iec_assert_data jsr iec_wait60us @@ -38,6 +46,9 @@ iec_rx_clk_wait: jmp iec_rx_clk_wait * + inc $0633 + + ;; CLK is now low. Latch input bits in on rising edge ;; of CLK, eight times for eight bits. ldx #7 @@ -45,9 +56,15 @@ iec_rx_clk_wait: lda #$00 php -iec_rx_bit_loop: +iec_rx_bit_loop: + + inc $0634 + ;; Wait for CLK to release jsr iec_wait_for_clock_release + + inc $0635 + ;; DATA now has the next bit, but inverted. ;; DATA is in bit6, which is a bit annoying. ;; But we can clock it out with two ROL instructions @@ -66,10 +83,14 @@ iec_rx_bit_loop: ;; Wait for CLK to re-assert jsr iec_wait_for_clock_assert + inc $0636 + ;; More bits? dex bpl iec_rx_bit_loop + inc $0637 + ;; Then we must within 1000usec acknowledge the frame by ;; asserting DATA. At this point, CLK is asserted by the ;; talker and DATA by us, i.e., we are ready to receive