From a70efc1fa04779aa698a4d723895d55c62091b9c Mon Sep 17 00:00:00 2001 From: FeralChild64 Date: Thu, 31 Dec 2020 19:49:38 +0100 Subject: [PATCH] Z80 cleanup --- src/zvm_m65/,aliases_zvm.s | 23 +++++++++-------- src/zvm_m65/Z80_instr_shftrot_RL.s | 2 +- src/zvm_m65/Z80_instr_shftrot_RLC.s | 2 +- src/zvm_m65/Z80_instr_shftrot_RR.s | 2 +- src/zvm_m65/Z80_instr_shftrot_RRC.s | 2 +- src/zvm_m65/Z80_instr_shftrot_SLA.s | 2 +- src/zvm_m65/Z80_instr_shftrot_SLL.s | 2 +- src/zvm_m65/Z80_instr_shftrot_SRA.s | 2 +- src/zvm_m65/Z80_instr_shftrot_SRL.s | 2 +- src/zvm_m65/z80_instr_bit.s | 32 +++++++++++------------ src/zvm_m65/z80_instr_math_8bit.s | 4 +-- src/zvm_m65/z80_instr_rotate_shift.s | 4 +-- src/zvm_m65/z80_reset.s | 38 ++++++++++++++++++++++++++++ src/zvm_m65/zvm_banking.s | 15 ++++++++--- src/zvm_m65/zvm_bios.s | 23 ++--------------- 15 files changed, 92 insertions(+), 63 deletions(-) create mode 100644 src/zvm_m65/z80_reset.s diff --git a/src/zvm_m65/,aliases_zvm.s b/src/zvm_m65/,aliases_zvm.s index cc497eb9..74a704cd 100644 --- a/src/zvm_m65/,aliases_zvm.s +++ b/src/zvm_m65/,aliases_zvm.s @@ -96,17 +96,18 @@ !addr VEC_fetch_via_DE = $4A !addr VEC_store_via_DE = $4C !addr VEC_fetch_via_HL = $4E -!addr VEC_store_via_HL = $50 -!addr VEC_fetch_via_IX_d = $52 -!addr VEC_fetch_via_IY_d = $54 -!addr VEC_store_via_IX_d = $56 -!addr VEC_store_via_IY_d = $58 -!addr VEC_fetch_via_nn = $5A -!addr VEC_store_via_nn = $5C -!addr VEC_fetch_via_plus1 = $5E -!addr VEC_store_via_plus1 = $60 ; XXX jump to next directly? -!addr VEC_xchng_stack_lo = $62 -!addr VEC_xchng_stack_hi = $64 +!addr VEC_fetch_via_HL_back = $50 ; forces PTR_DATA update +!addr VEC_store_via_HL = $52 +!addr VEC_fetch_via_IX_d = $54 +!addr VEC_fetch_via_IY_d = $56 +!addr VEC_store_via_IX_d = $58 +!addr VEC_store_via_IY_d = $5A +!addr VEC_fetch_via_nn = $5C +!addr VEC_store_via_nn = $5E +!addr VEC_fetch_via_plus1 = $60 +!addr VEC_store_via_plus1 = $62 ; XXX jump to next directly? +!addr VEC_xchng_stack_lo = $64 +!addr VEC_xchng_stack_hi = $68 ; ; Constant/macros definitions diff --git a/src/zvm_m65/Z80_instr_shftrot_RL.s b/src/zvm_m65/Z80_instr_shftrot_RL.s index 1c0ce575..fbad73fc 100644 --- a/src/zvm_m65/Z80_instr_shftrot_RL.s +++ b/src/zvm_m65/Z80_instr_shftrot_RL.s @@ -18,7 +18,7 @@ !macro Z80_RL_VIA_HL { - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) clc bbr0 REG_F, @1 diff --git a/src/zvm_m65/Z80_instr_shftrot_RLC.s b/src/zvm_m65/Z80_instr_shftrot_RLC.s index daae23fe..e49a94f4 100644 --- a/src/zvm_m65/Z80_instr_shftrot_RLC.s +++ b/src/zvm_m65/Z80_instr_shftrot_RLC.s @@ -18,7 +18,7 @@ !macro Z80_RLC_VIA_HL { - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) tax rol diff --git a/src/zvm_m65/Z80_instr_shftrot_RR.s b/src/zvm_m65/Z80_instr_shftrot_RR.s index 4b22d3e5..0255deca 100644 --- a/src/zvm_m65/Z80_instr_shftrot_RR.s +++ b/src/zvm_m65/Z80_instr_shftrot_RR.s @@ -18,7 +18,7 @@ !macro Z80_RR_VIA_HL { - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) clc bbr0 REG_F, @1 diff --git a/src/zvm_m65/Z80_instr_shftrot_RRC.s b/src/zvm_m65/Z80_instr_shftrot_RRC.s index 9a9cda3a..7fac5954 100644 --- a/src/zvm_m65/Z80_instr_shftrot_RRC.s +++ b/src/zvm_m65/Z80_instr_shftrot_RRC.s @@ -18,7 +18,7 @@ !macro Z80_RRC_VIA_HL { - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) tax ror diff --git a/src/zvm_m65/Z80_instr_shftrot_SLA.s b/src/zvm_m65/Z80_instr_shftrot_SLA.s index 5e521374..23bb6723 100644 --- a/src/zvm_m65/Z80_instr_shftrot_SLA.s +++ b/src/zvm_m65/Z80_instr_shftrot_SLA.s @@ -14,7 +14,7 @@ !macro Z80_SLA_VIA_HL { - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) asl sta [PTR_DATA],z diff --git a/src/zvm_m65/Z80_instr_shftrot_SLL.s b/src/zvm_m65/Z80_instr_shftrot_SLL.s index e43ac29d..f784220a 100644 --- a/src/zvm_m65/Z80_instr_shftrot_SLL.s +++ b/src/zvm_m65/Z80_instr_shftrot_SLL.s @@ -15,7 +15,7 @@ !macro Z80_SLL_VIA_HL { - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) sec rol diff --git a/src/zvm_m65/Z80_instr_shftrot_SRA.s b/src/zvm_m65/Z80_instr_shftrot_SRA.s index 86656539..1b8b3197 100644 --- a/src/zvm_m65/Z80_instr_shftrot_SRA.s +++ b/src/zvm_m65/Z80_instr_shftrot_SRA.s @@ -18,7 +18,7 @@ !macro Z80_SRA_VIA_HL { - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) tax ror diff --git a/src/zvm_m65/Z80_instr_shftrot_SRL.s b/src/zvm_m65/Z80_instr_shftrot_SRL.s index ff9e415f..4e6091ea 100644 --- a/src/zvm_m65/Z80_instr_shftrot_SRL.s +++ b/src/zvm_m65/Z80_instr_shftrot_SRL.s @@ -15,7 +15,7 @@ !macro Z80_SRL_VIA_HL { - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) clc ror diff --git a/src/zvm_m65/z80_instr_bit.s b/src/zvm_m65/z80_instr_bit.s index bec34ddd..4028b13f 100644 --- a/src/zvm_m65/z80_instr_bit.s +++ b/src/zvm_m65/z80_instr_bit.s @@ -872,49 +872,49 @@ Z80_instr_CB_FF: ; SET 7,A Z80_instr_CB_C6: ; SET 0,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) ora #%00000001 jmp ZVM_store_next Z80_instr_CB_CE: ; SET 1,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) ora #%00000010 jmp ZVM_store_next Z80_instr_CB_D6: ; SET 2,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) ora #%00000100 jmp ZVM_store_next Z80_instr_CB_DE: ; SET 3,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) ora #%00001000 jmp ZVM_store_next Z80_instr_CB_E6: ; SET 4,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) ora #%00010000 jmp ZVM_store_next Z80_instr_CB_EE: ; SET 5,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) ora #%00100000 jmp ZVM_store_next Z80_instr_CB_F6: ; SET 6,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) ora #%01000000 jmp ZVM_store_next Z80_instr_CB_FE: ; SET 7,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) ora #%10000000 jmp ZVM_store_next @@ -1256,49 +1256,49 @@ Z80_instr_CB_BF: ; RES 7,A Z80_instr_CB_86: ; RES 0,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) and #%11111110 jmp ZVM_store_next Z80_instr_CB_8E: ; RES 1,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) and #%11111101 jmp ZVM_store_next Z80_instr_CB_96: ; RES 2,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) and #%11111011 jmp ZVM_store_next Z80_instr_CB_9E: ; RES 3,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) and #%11110111 jmp ZVM_store_next Z80_instr_CB_A6: ; RES 4,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) and #%11101111 jmp ZVM_store_next Z80_instr_CB_AE: ; RES 5,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) and #%11011111 jmp ZVM_store_next Z80_instr_CB_B6: ; RES 6,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) and #%10111111 jmp ZVM_store_next Z80_instr_CB_BE: ; RES 7,(HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) and #%01111111 jmp ZVM_store_next diff --git a/src/zvm_m65/z80_instr_math_8bit.s b/src/zvm_m65/z80_instr_math_8bit.s index 66b3cd4c..d967cb5f 100644 --- a/src/zvm_m65/z80_instr_math_8bit.s +++ b/src/zvm_m65/z80_instr_math_8bit.s @@ -612,7 +612,7 @@ Z80_common_INC: Z80_instr_34: ; INC (HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) tax inc sta [PTR_DATA],z @@ -668,7 +668,7 @@ Z80_common_DEC: Z80_instr_35: ; DEC (HL) - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) tax dec sta [PTR_DATA],z diff --git a/src/zvm_m65/z80_instr_rotate_shift.s b/src/zvm_m65/z80_instr_rotate_shift.s index cfb52447..5ed5703d 100644 --- a/src/zvm_m65/z80_instr_rotate_shift.s +++ b/src/zvm_m65/z80_instr_rotate_shift.s @@ -8,7 +8,7 @@ Z80_instr_ED_67: ; RRD - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) sta REG_TMP1 lda REG_A @@ -47,7 +47,7 @@ Z80_instr_ED_67: ; RRD Z80_instr_ED_6F: ; RLD - jsr (VEC_fetch_via_HL) + jsr (VEC_fetch_via_HL_back) sta REG_TMP1 lda REG_A diff --git a/src/zvm_m65/z80_reset.s b/src/zvm_m65/z80_reset.s new file mode 100644 index 00000000..ac66a915 --- /dev/null +++ b/src/zvm_m65/z80_reset.s @@ -0,0 +1,38 @@ + +; +; Z80 CPU reset +; + + +Z80_reset: + + ; Reset registers and internal emulation data + + lda #$00 + tay +@1: + sta z80_cpustate__start, y + iny + cmp #(z80_cpustate__end - z80_cpustate__start + 1) + bne @1 + + dew REG_AF ; AF and SP have $FFFF value at start + dew REG_SP + + lda TIME+2 ; give a little initial randomness to register R + sta REG_R06 + + ; The engine requires all the Z80 visible memory to be present within the 1st 16MB, + ; so set the most significant buytes of 32-bit pointers to 0. + + stz REG_BC_EXT1+1 + stz REG_DE_EXT1+1 + stz REG_HL_EXT1+1 + stz REG_SP_EXT1+1 + stz REG_PC_EXT1+1 + stz PTR_IXY_d_EXT1+1 + stz PTR_DATA_EXT1+1 + + ; Default bank is 1 (the fastest, continuous memory) + + jmp ZVM_set_bank_1 diff --git a/src/zvm_m65/zvm_banking.s b/src/zvm_m65/zvm_banking.s index 4d8bfcab..54eaaa54 100644 --- a/src/zvm_m65/zvm_banking.s +++ b/src/zvm_m65/zvm_banking.s @@ -34,9 +34,18 @@ ZVM_set_bank_1: ; XXX use DMAgic to switch banks (vectors on zeropage) - lda #$04 ; all the Z80 bank 1 memory is located in $0004:$xxxx - sta PTR_DATA+2 - sta PTR_IXY_d+2 + ; Since all the Z80 bank 1 memory is located in $0005:$xxxx, + ; we can set some bytes in certain pointers for faster execution + + lda #$05 + + sta REG_BC_EXT1+0 + sta REG_DE_EXT1+0 + sta REG_HL_EXT1+0 + sta REG_SP_EXT1+0 + sta REG_PC_EXT1+0 + sta PTR_IXY_d_EXT1+0 + sta PTR_DATA_EXT1+0 rts diff --git a/src/zvm_m65/zvm_bios.s b/src/zvm_m65/zvm_bios.s index b11d375b..86d6b7f4 100644 --- a/src/zvm_m65/zvm_bios.s +++ b/src/zvm_m65/zvm_bios.s @@ -53,30 +53,11 @@ zvm_BIOS_00_BOOT: ; Cold start ; XXX !!! - ; XXX fetch RAM disk image + ; XXX fetch RAM disk image, CPM3.SYS, command interpreter ; XXX close all the files, reset I/O, set screen mode ; XXX clear memory - ; Reset registers and internal emulation data - - ldz #$00 ; .Z is required to be 0 all the time - lda #$00 - tay -@1: - sta REG_AF, y - iny - cmp #(REG_IFF2+1) - bne @1 - - dew REG_AF ; AF and SP have $FFFF value on start - dew REG_SP - - lda TIME+2 ; give a little initial randomness to register R - sta REG_R06 - - ; XXX restore all *_EXT1 values - - ; XXX load CPM3.SYS + jsr Z80_reset ; FALLTROUGH