From b79f01582d7a51d4ab16def8740cd4a4fe797463 Mon Sep 17 00:00:00 2001 From: FeralChild64 Date: Tue, 22 Dec 2020 19:29:36 +0100 Subject: [PATCH] code size optimization --- src/zvm_m65/2000.zvm_vectable.s | 120 +++-------- src/zvm_m65/z80_instr_bit.s | 353 ++++++++++---------------------- src/zvm_m65/zvm_core.s | 47 ++--- 3 files changed, 156 insertions(+), 364 deletions(-) diff --git a/src/zvm_m65/2000.zvm_vectable.s b/src/zvm_m65/2000.zvm_vectable.s index 9ad98e99..7c12fe9c 100644 --- a/src/zvm_m65/2000.zvm_vectable.s +++ b/src/zvm_m65/2000.zvm_vectable.s @@ -271,106 +271,54 @@ Z80_vectab_FD_1: !word Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD !word Z80_illegal__FD, Z80_instr_FD_F9, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD, Z80_illegal__FD -Z80_vectab_DDCB_0: +Z80_vectab_xDCB_0: - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_06, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_0E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_06, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_0E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_16, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_1E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_16, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_1E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_26, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_2E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_26, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_2E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_3E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_3E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_46, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_4E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_46, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_4E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_56, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_5E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_56, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_5E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_66, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_6E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_66, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_6E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_76, Z80_illegal__DDCB - !word Z80_illeg_DDCB_78, Z80_illeg_DDCB_79, Z80_illeg_DDCB_7A, Z80_illeg_DDCB_7B, Z80_illeg_DDCB_7C, Z80_illeg_DDCB_7D, Z80_instr_DDCB_7E, Z80_illeg_DDCB_7F + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_76, Z80_illegal__xDCB + !word Z80_illeg_xDCB_78, Z80_illeg_xDCB_79, Z80_illeg_xDCB_7A, Z80_illeg_xDCB_7B, Z80_illeg_xDCB_7C, Z80_illeg_xDCB_7D, Z80_instr_xDCB_7E, Z80_illeg_xDCB_7F -Z80_vectab_DDCB_1: +Z80_vectab_xDCB_1: - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_86, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_8E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_86, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_8E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_96, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_9E, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_96, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_9E, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_A6, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_AE, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_A6, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_AE, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_B6, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_BE, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_B6, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_BE, Z80_illegal__xDCB - !word Z80_illeg_DDCB_C0, Z80_illeg_DDCB_C1, Z80_illeg_DDCB_C2, Z80_illeg_DDCB_C3, Z80_illeg_DDCB_C4, Z80_illeg_DDCB_C5, Z80_instr_DDCB_C6, Z80_illeg_DDCB_C7 - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_CE, Z80_illegal__DDCB + !word Z80_illeg_xDCB_C0, Z80_illeg_xDCB_C1, Z80_illeg_xDCB_C2, Z80_illeg_xDCB_C3, Z80_illeg_xDCB_C4, Z80_illeg_xDCB_C5, Z80_instr_xDCB_C6, Z80_illeg_xDCB_C7 + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_CE, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_D6, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_DE, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_D6, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_DE, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_E6, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_EE, Z80_illegal__DDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_E6, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_EE, Z80_illegal__xDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_F6, Z80_illegal__DDCB - !word Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_illegal__DDCB, Z80_instr_DDCB_FE, Z80_illegal__DDCB - -Z80_vectab_FDCB_0: - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_06, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_0E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_16, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_1E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_26, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_2E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_3E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_46, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_4E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_56, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_5E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_66, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_6E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_76, Z80_illegal__FDCB - !word Z80_illeg_FDCB_78, Z80_illeg_FDCB_79, Z80_illeg_FDCB_7A, Z80_illeg_FDCB_7B, Z80_illeg_FDCB_7C, Z80_illeg_FDCB_7D, Z80_instr_FDCB_7E, Z80_illeg_FDCB_7F - -Z80_vectab_FDCB_1: - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_86, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_8E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_96, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_9E, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_A6, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_AE, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_B6, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_BE, Z80_illegal__FDCB - - !word Z80_illeg_FDCB_C0, Z80_illeg_FDCB_C1, Z80_illeg_FDCB_C2, Z80_illeg_FDCB_C3, Z80_illeg_FDCB_C4, Z80_illeg_FDCB_C5, Z80_instr_FDCB_C6, Z80_illeg_FDCB_C7 - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_CE, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_D6, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_DE, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_E6, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_EE, Z80_illegal__FDCB - - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_F6, Z80_illegal__FDCB - !word Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_illegal__FDCB, Z80_instr_FDCB_FE, Z80_illegal__FDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_F6, Z80_illegal__xDCB + !word Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_illegal__xDCB, Z80_instr_xDCB_FE, Z80_illegal__xDCB diff --git a/src/zvm_m65/z80_instr_bit.s b/src/zvm_m65/z80_instr_bit.s index 8b086c9d..25796f06 100644 --- a/src/zvm_m65/z80_instr_bit.s +++ b/src/zvm_m65/z80_instr_bit.s @@ -440,71 +440,71 @@ Z80_common_bitHL_1: ; bits taken from index register + displacement -Z80_instr_DDCB_46: ; BIT 0,(IX+d) +Z80_instr_xDCB_46: ; BIT 0,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%00000001 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 + bne Z80_common_bitIXYx_1 + bra Z80_common_bitIXYx_0 -Z80_instr_DDCB_4E: ; BIT 1,(IX+d) +Z80_instr_xDCB_4E: ; BIT 1,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%00000010 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 + bne Z80_common_bitIXYx_1 + bra Z80_common_bitIXYx_0 -Z80_instr_DDCB_56: ; BIT 2,(IX+d) +Z80_instr_xDCB_56: ; BIT 2,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%00000100 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 + bne Z80_common_bitIXYx_1 + bra Z80_common_bitIXYx_0 -Z80_instr_DDCB_5E: ; BIT 3,(IX+d) +Z80_instr_xDCB_5E: ; BIT 3,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%00001000 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 + bne Z80_common_bitIXYx_1 + bra Z80_common_bitIXYx_0 -Z80_instr_DDCB_66: ; BIT 4,(IX+d) +Z80_instr_xDCB_66: ; BIT 4,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%00010000 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 + bne Z80_common_bitIXYx_1 + bra Z80_common_bitIXYx_0 -Z80_instr_DDCB_6E: ; BIT 5,(IX+d) +Z80_instr_xDCB_6E: ; BIT 5,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%00100000 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 + bne Z80_common_bitIXYx_1 + bra Z80_common_bitIXYx_0 -Z80_instr_DDCB_76: ; BIT 6,(IX+d) +Z80_instr_xDCB_76: ; BIT 6,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%01000000 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 + bne Z80_common_bitIXYx_1 + bra Z80_common_bitIXYx_0 -Z80_illeg_DDCB_78: ; BIT 7,(IX+d) -Z80_illeg_DDCB_79: ; BIT 7,(IX+d) -Z80_illeg_DDCB_7A: ; BIT 7,(IX+d) -Z80_illeg_DDCB_7B: ; BIT 7,(IX+d) -Z80_illeg_DDCB_7C: ; BIT 7,(IX+d) -Z80_illeg_DDCB_7D: ; BIT 7,(IX+d) -Z80_instr_DDCB_7E: ; BIT 7,(IX+d) -Z80_illeg_DDCB_7F: ; BIT 7,(IX+d) +Z80_illeg_xDCB_78: ; BIT 7,(IXY+d) +Z80_illeg_xDCB_79: ; BIT 7,(IXY+d) +Z80_illeg_xDCB_7A: ; BIT 7,(IXY+d) +Z80_illeg_xDCB_7B: ; BIT 7,(IXY+d) +Z80_illeg_xDCB_7C: ; BIT 7,(IXY+d) +Z80_illeg_xDCB_7D: ; BIT 7,(IXY+d) +Z80_instr_xDCB_7E: ; BIT 7,(IXY+d) +Z80_illeg_xDCB_7F: ; BIT 7,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%10000000 - beq Z80_common_bitXYx_0 + beq Z80_common_bitIXYx_0 ; FALLTROUGH -Z80_common_bitXY7_1: +Z80_common_bitIXY7_1: lda REG_F and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_ZF - Z80_PF) @@ -516,7 +516,7 @@ Z80_common_bitXY7_1: sta REG_F jmp ZVM_next -Z80_common_bitXYx_0: +Z80_common_bitIXYx_0: lda REG_F and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF) @@ -528,7 +528,7 @@ Z80_common_bitXYx_0: sta REG_F jmp ZVM_next -Z80_common_bitXYx_1: +Z80_common_bitIXYx_1: lda REG_F and #($FF - Z80_NF - Z80_XF - Z80_YF - Z80_SF - Z80_ZF - Z80_PF) @@ -540,69 +540,6 @@ Z80_common_bitXYx_1: sta REG_F jmp ZVM_next -Z80_instr_FDCB_46: ; BIT 0,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%00000001 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 - -Z80_instr_FDCB_4E: ; BIT 1,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%00000010 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 - -Z80_instr_FDCB_56: ; BIT 2,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%00000100 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 - -Z80_instr_FDCB_5E: ; BIT 3,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%00001000 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 - -Z80_instr_FDCB_66: ; BIT 4,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%00010000 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 - -Z80_instr_FDCB_6E: ; BIT 5,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%00100000 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 - -Z80_instr_FDCB_76: ; BIT 6,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%01000000 - bne Z80_common_bitXYx_1 - bra Z80_common_bitXYx_0 - -Z80_illeg_FDCB_78: ; BIT 7,(IY+d) -Z80_illeg_FDCB_79: ; BIT 7,(IY+d) -Z80_illeg_FDCB_7A: ; BIT 7,(IY+d) -Z80_illeg_FDCB_7B: ; BIT 7,(IY+d) -Z80_illeg_FDCB_7C: ; BIT 7,(IY+d) -Z80_illeg_FDCB_7D: ; BIT 7,(IY+d) -Z80_instr_FDCB_7E: ; BIT 7,(IY+d) -Z80_illeg_FDCB_7F: ; BIT 7,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%10000000 - +bne Z80_common_bitXY7_1 ; too far away for normal BNE - bra Z80_common_bitXYx_0 - ; SET, RES Z80_instr_CB_C0: ; SET 0,B @@ -933,101 +870,61 @@ Z80_instr_CB_FE: ; SET 7,(HL) ora #%10000000 jmp ZVM_store_next -Z80_instr_DDCB_C6: ; SET 0,(IX+d) +Z80_instr_xDCB_C6: ; SET 0,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z ora #%00000001 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_CE: ; SET 1,(IX+d) +Z80_instr_xDCB_CE: ; SET 1,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z ora #%00000010 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_D6: ; SET 2,(IX+d) +Z80_instr_xDCB_D6: ; SET 2,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z ora #%00000100 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_DE: ; SET 3,(IX+d) +Z80_instr_xDCB_DE: ; SET 3,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z ora #%00001000 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_E6: ; SET 4,(IX+d) +Z80_instr_xDCB_E6: ; SET 4,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z ora #%00010000 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_EE: ; SET 5,(IX+d) +Z80_instr_xDCB_EE: ; SET 5,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z ora #%00100000 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_F6: ; SET 6,(IX+d) +Z80_instr_xDCB_F6: ; SET 6,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z ora #%01000000 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_FE: ; SET 7,(IX+d) +Z80_instr_xDCB_FE: ; SET 7,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z ora #%10000000 - jmp ZVM_store_next - -Z80_instr_FDCB_C6: ; SET 0,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00000001 - jmp ZVM_store_next - -Z80_instr_FDCB_CE: ; SET 1,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00000010 - jmp ZVM_store_next - -Z80_instr_FDCB_D6: ; SET 2,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00000100 - jmp ZVM_store_next - -Z80_instr_FDCB_DE: ; SET 3,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00001000 - jmp ZVM_store_next - -Z80_instr_FDCB_E6: ; SET 4,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00010000 - jmp ZVM_store_next - -Z80_instr_FDCB_EE: ; SET 5,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%00100000 - jmp ZVM_store_next - -Z80_instr_FDCB_F6: ; SET 6,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%01000000 - jmp ZVM_store_next - -Z80_instr_FDCB_FE: ; SET 7,(IY+d) - - jsr (VEC_fetch_via_IY_d) - ora #%10000000 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next Z80_instr_CB_80: ; RES 0,B @@ -1357,98 +1254,58 @@ Z80_instr_CB_BE: ; RES 7,(HL) and #%01111111 jmp ZVM_store_next -Z80_instr_DDCB_86: ; RES 0,(IX+d) +Z80_instr_xDCB_86: ; RES 0,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%11111110 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_8E: ; RES 1,(IX+d) +Z80_instr_xDCB_8E: ; RES 1,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%11111101 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_96: ; RES 2,(IX+d) +Z80_instr_xDCB_96: ; RES 2,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%11111011 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_9E: ; RES 3,(IX+d) +Z80_instr_xDCB_9E: ; RES 3,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%11110111 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_A6: ; RES 4,(IX+d) +Z80_instr_xDCB_A6: ; RES 4,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%11101111 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_AE: ; RES 5,(IX+d) +Z80_instr_xDCB_AE: ; RES 5,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%11011111 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_B6: ; RES 6,(IX+d) +Z80_instr_xDCB_B6: ; RES 6,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%10111111 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next -Z80_instr_DDCB_BE: ; RES 7,(IX+d) +Z80_instr_xDCB_BE: ; RES 7,(IXY+d) - jsr (VEC_fetch_via_IX_d) + lda [PTR_IXY_d],z and #%01111111 - jmp ZVM_store_next - -Z80_instr_FDCB_86: ; RES 0,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11111110 - jmp ZVM_store_next - -Z80_instr_FDCB_8E: ; RES 1,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11111101 - jmp ZVM_store_next - -Z80_instr_FDCB_96: ; RES 2,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11111011 - jmp ZVM_store_next - -Z80_instr_FDCB_9E: ; RES 3,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11110111 - jmp ZVM_store_next - -Z80_instr_FDCB_A6: ; RES 4,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11101111 - jmp ZVM_store_next - -Z80_instr_FDCB_AE: ; RES 5,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%11011111 - jmp ZVM_store_next - -Z80_instr_FDCB_B6: ; RES 6,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%10111111 - jmp ZVM_store_next - -Z80_instr_FDCB_BE: ; RES 7,(IY+d) - - jsr (VEC_fetch_via_IY_d) - and #%01111111 - jmp ZVM_store_next + sta [PTR_IXY_d],z + jmp ZVM_next diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s index addeb42a..5ac4ac87 100644 --- a/src/zvm_m65/zvm_core.s +++ b/src/zvm_m65/zvm_core.s @@ -31,8 +31,8 @@ ZVM_store_next: Z80_illegal__DD: Z80_illegal__ED: Z80_illegal__FD: -Z80_illegal__DDCB: -Z80_illegal__FDCB: +Z80_illegal__xDCB: + ; XXX add a separate handler for illegal instructions ; LD instructions with no effect Z80_instr_40: ; LD B,B Z80_instr_49: ; LD C,C @@ -330,20 +330,13 @@ Z80_instr_FD_9E: ; SBC (IY+d) Z80_instr_FD_BE: ; CP (IY+d) Z80_instr_FD_E3: ; EX (SP),IY Z80_instr_FD_F9: ; LD SP,IY -Z80_instr_DDCB_06: ; RLC (IX+d) -Z80_instr_DDCB_0E: ; RRC (IX+d) -Z80_instr_DDCB_16: ; RL (IX+d) -Z80_instr_DDCB_1E: ; RR (IX+d) -Z80_instr_DDCB_26: ; SLA (IX+d) -Z80_instr_DDCB_2E: ; SRA (IX+d) -Z80_instr_DDCB_3E: ; SRL (IX+d) -Z80_instr_FDCB_06: ; RLC (IY+d) -Z80_instr_FDCB_0E: ; RRC (IY+d) -Z80_instr_FDCB_16: ; RL (IY+d) -Z80_instr_FDCB_1E: ; RR (IY+d) -Z80_instr_FDCB_26: ; SLA (IY+d) -Z80_instr_FDCB_2E: ; SRA (IY+d) -Z80_instr_FDCB_3E: ; SRL (IY+d) +Z80_instr_xDCB_06: ; RLC (IXY+d) +Z80_instr_xDCB_0E: ; RRC (IXY+d) +Z80_instr_xDCB_16: ; RL (IXY+d) +Z80_instr_xDCB_1E: ; RR (IXY+d) +Z80_instr_xDCB_26: ; SLA (IXY+d) +Z80_instr_xDCB_2E: ; SRA (IXY+d) +Z80_instr_xDCB_3E: ; SRL (IXY+d) Z80_illeg_CB_30: ; SLL B Z80_illeg_CB_31: ; SLL C Z80_illeg_CB_32: ; SLL D @@ -367,20 +360,14 @@ Z80_illeg_ED_74: ; NEG Z80_illeg_ED_75: ; RETN Z80_illeg_ED_7C: ; NEG Z80_illeg_ED_7D: ; RETN -Z80_illeg_DDCB_C0: ; SET 0,(IX+d),B -Z80_illeg_DDCB_C1: ; SET 0,(IX+d),C -Z80_illeg_DDCB_C2: ; SET 0,(IX+d),D -Z80_illeg_DDCB_C3: ; SET 0,(IX+d),E -Z80_illeg_DDCB_C4: ; SET 0,(IX+d),H -Z80_illeg_DDCB_C5: ; SET 0,(IX+d),L -Z80_illeg_DDCB_C7: ; SET 0,(IX+d),A -Z80_illeg_FDCB_C0: ; SET 0,(IY+d),B -Z80_illeg_FDCB_C1: ; SET 0,(IY+d),C -Z80_illeg_FDCB_C2: ; SET 0,(IY+d),D -Z80_illeg_FDCB_C3: ; SET 0,(IY+d),E -Z80_illeg_FDCB_C4: ; SET 0,(IY+d),H -Z80_illeg_FDCB_C5: ; SET 0,(IY+d),L -Z80_illeg_FDCB_C7: ; SET 0,(IY+d),A +Z80_illeg_xDCB_C0: ; SET 0,(IXY+d),B +Z80_illeg_xDCB_C1: ; SET 0,(IXY+d),C +Z80_illeg_xDCB_C2: ; SET 0,(IXY+d),D +Z80_illeg_xDCB_C3: ; SET 0,(IXY+d),E +Z80_illeg_xDCB_C4: ; SET 0,(IXY+d),H +Z80_illeg_xDCB_C5: ; SET 0,(IXY+d),L +Z80_illeg_xDCB_C7: ; SET 0,(IXY+d),A + jmp ZVM_next ; XXX