implemented NEG
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@@ -270,7 +270,6 @@ Z80_instr_DD_E3: ; EX (SP),IX
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Z80_instr_DD_F9: ; LD SP,IX
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Z80_instr_ED_42: ; SBC HL,BC
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Z80_instr_ED_43: ; LD (nn),BC
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Z80_instr_ED_44: ; NEG
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Z80_instr_ED_45: ; RETN
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Z80_instr_ED_4A: ; ADC HL,BC
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Z80_instr_ED_4B: ; LD BC,(nn)
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@@ -345,20 +344,13 @@ Z80_illeg_CB_34: ; SLL H
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Z80_illeg_CB_35: ; SLL L
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Z80_illeg_CB_36: ; SLL (HL)
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Z80_illeg_CB_37: ; SLL A
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Z80_illeg_ED_4C: ; NEG
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Z80_illeg_ED_54: ; NEG
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Z80_illeg_ED_55: ; RETN
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Z80_illeg_ED_5C: ; NEG
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Z80_illeg_ED_5D: ; RETN
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Z80_illeg_ED_64: ; NEG
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Z80_illeg_ED_65: ; RETN
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Z80_illeg_ED_6C: ; NEG
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Z80_illeg_ED_6D: ; RETN
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Z80_illeg_ED_70: ; IN F,(C)
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Z80_illeg_ED_71: ; OUT (C),0
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Z80_illeg_ED_74: ; NEG
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Z80_illeg_ED_75: ; RETN
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Z80_illeg_ED_7C: ; NEG
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Z80_illeg_ED_7D: ; RETN
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Z80_illeg_xDCB_C0: ; SET 0,(IXY+d),B
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Z80_illeg_xDCB_C1: ; SET 0,(IXY+d),C
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