From c2375f7ce4bb9b1ed7b33b857efc22860e702ca0 Mon Sep 17 00:00:00 2001
From: FeralChild64 <you@example.com>
Date: Sun, 3 Nov 2019 11:08:17 +0100
Subject: [PATCH] initial badline synchronization for JiffyDOS

---
 c64/kernal/iec/f000.iec_jiffydos.s | 67 ++++++++++++++++++++++++------
 1 file changed, 55 insertions(+), 12 deletions(-)

diff --git a/c64/kernal/iec/f000.iec_jiffydos.s b/c64/kernal/iec/f000.iec_jiffydos.s
index 1b7aec4d..2448e2f4 100644
--- a/c64/kernal/iec/f000.iec_jiffydos.s
+++ b/c64/kernal/iec/f000.iec_jiffydos.s
@@ -12,36 +12,76 @@
 
 iec_tx_byte_jiffydos:
 
+	// XXX disable screen - temporary, just for testing
+	tay
+	lda VIC_SCROLY
+	and #($FF - $10)
+	sta VIC_SCROLY
+	lda VIC_RASTER
+!:
+	cmp VIC_RASTER
+	beq !-
+	tya
+
 	// JiffyDOS timing regime is very strict - before transmitting anything
 	// we need to disable sprites and (if screen is not disabled) wait for
 	// appropriate moment, so that no badline interruption can happen
 	
 	jsr jiffydos_hide_sprites
+	pha                                // store previous sprite status on stack
 	jsr jiffydos_wait_line
 
 __jd_check1:
 
+
 	// XXX send byte
 
+
 	// Re-enable sprites
-	jsr jiffydos_restore_sprites
+	pla
+	lda VIC_SPENA
+
+	// XXX reenable screen - temporary, just for testing
+	lda VIC_SCROLY
+	ora #$10
+	sta VIC_SCROLY
 
 	rts
 	
 
 iec_rx_byte_jiffydos:
 
+	// XXX disable screen - temporary, just for testing
+	lda VIC_SCROLY
+	and #($FF - $10)
+	sta VIC_SCROLY
+	lda VIC_RASTER
+!:
+	cmp VIC_RASTER
+	beq !-
+
 	// JiffyDOS timing regime is very strict - before transmitting anything
 	// we need to disable sprites and (if screen is not disabled) wait for
 	// appropriate moment, so that no badline interruption can happen
 	
 	jsr jiffydos_hide_sprites
+	pha                                // store previous sprite status on stack
 	jsr jiffydos_wait_line
 
+
 	// XXX retrieve byte
 
+
 	// Re-enable sprites
-	jsr jiffydos_restore_sprites
+	pla
+	lda VIC_SPENA
+
+	// XXX reenable screen - temporary, just for testing
+	tay
+	lda VIC_SCROLY
+	ora #$10
+	sta VIC_SCROLY
+	tya
 
 	rts
 
@@ -52,11 +92,19 @@ jiffydos_wait_line:
 	and #$10
 	beq jiffydos_wait_line_done        // screen is disabled, no need to watch for badlines
 
-	// XXX wait for badline to pass
+	// To give the transfer routine as much time as possible,
+	// wait till a badline
 
+	// XXX this has to be carefully tested!
+!:
+	sec
+	lda VIC_SCROLY
+	sbc VIC_RASTER
+	and #$07                           // we want 8 lowest bits
+	bne !-
 
 jiffydos_wait_line_done:
-	rts
+	rts                                // XXX 6 cycles... we might be forced to inline this routine
 
 
 __jd_check2:
@@ -64,14 +112,9 @@ __jd_check2:
 	
 jiffydos_hide_sprites:
 
-	// XXX implement
-	
-	rts
-
-
-jiffydos_restore_sprites:
-
-	// XXX implement
+	lda VIC_SPENA
+	ldx #$00
+	stx VIC_SPENA
 	
 	rts