chris/open-roms
1
0 Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

migrated to ACME assembler

Browse Source 
commit 145d64aa6e78838ed07cefed372f0ad6a4687e97
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 20:16:57 2020 +0200

    ACME adaptation

commit 885209d7822286744ea53232ae7461472a01d5d6
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 19:57:25 2020 +0200

    ACME adaptation

commit 334d84486bc603551887e7cbeb59d329f2224cc7
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 18:29:15 2020 +0200

    ACME adaptation

commit b5966f49bcd8f0ca79cbec93819a31238924707e
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 18:09:31 2020 +0200

    ACME adaptation

commit 786536a93a5eab5e676fca99625b4eb094a554e7
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 17:24:48 2020 +0200

    ACME adaptation

commit 704c70dfb1f5d68775d6f3da220803b8a3990f56
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 15:07:12 2020 +0200

    ACME adaptation

commit 136874964c9083b375f151475310f9636871fc72
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 14:45:14 2020 +0200

    ACME adaptation

commit 8eca0d5700b72d04336e72c5cd3a68e18b85f96d
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 14:06:52 2020 +0200

    ACME adaptation

commit 11d29eb7ee318239d782f85498b6d0524624d5c4
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 13:56:45 2020 +0200

    ACME apaptation

commit c9b5e5e04cceb92c66bc027e6440bc0f7c5a499f
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 13:49:04 2020 +0200

    ACME adaptation

commit f5cc254cbc921f07863807468cb3fe26b410b409
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 13:01:18 2020 +0200

    ACME adaptation

commit e135a27bf9c30cc0965379c954564e06406303b1
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 19 21:55:01 2020 +0200

    ACME adaptation

commit e9dfddf90d9e2795e88b7da40ae050d733faeb56
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 19 21:48:47 2020 +0200

    Makefile fix

commit 07030104c65cf5e5beeacf6d629ccb9245e58657
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 19 21:42:00 2020 +0200

    ACME adaptation

commit f824362ee5bcfbffca86c430b57773b2ffd65655
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 19 20:14:56 2020 +0200

    ACME adaptation

commit 3a3c59007dcd4940d89b8669f34ca56b61c25fdf
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 18 21:51:45 2020 +0200

    ACME adaptation

commit 6790ef7bc88a41de2881c69b7524dd4ab8c74b5d
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 18 20:35:23 2020 +0200

    ACME adaptation

commit 38ad18b90e9ec713aa7ca49576b3388ce1733357
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 18 18:46:20 2020 +0200

    ACME adaptation

commit 541340371122a9702f7b2d9771c298223cffd0e9
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 18 16:49:46 2020 +0200

    ACME adaptation

commit 25cfd5e186459be1a260d3eb8cfff767838de370
Author: FeralChild64 <you@example.com>
Date:   Thu Sep 17 20:13:33 2020 +0200

    ACME adaptation

commit f61599444d5b1d03d8fd8e4a6a7c3b85069bedb3
Author: FeralChild64 <you@example.com>
Date:   Thu Sep 17 19:29:23 2020 +0200

    ACME adaptation

commit b290be31ec7bb2e5723607697da1bbc621c84429
Author: FeralChild64 <you@example.com>
Date:   Thu Sep 17 17:20:14 2020 +0200

    ACME adaptation

commit 877be9e856880d98fd4bcb25b42aaaacda9dc463
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 16 21:47:38 2020 +0200

    ACME adaptation

commit bb20edaf85d386e41d5c2f715b745b68fbd3362e
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 16 21:31:30 2020 +0200

    ACME adaptation

commit c5d31bd8685abce37c8e254d15aac20bd1570d9f
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 16 18:40:49 2020 +0200

    ACME adaptation

commit 29349826b38f8a89649171559dc8cf24c560aff1
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 23:35:47 2020 +0200

    ACME adaptation

commit 8bcd6a621c4b11766d0cf34f79858ba90a67248e
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 22:52:25 2020 +0200

    ACME adaptation

commit e87a69edc2ce4bfcc460c31e08dcc352a985f88d
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 22:43:27 2020 +0200

    ACME adaptation

commit f49a097bd52e96d00b866c02bda7121e4543233c
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 19:02:07 2020 +0200

    ACME adaptation

commit fa0e9214a633b8e8f867cc70925b390940dcd426
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 17:47:19 2020 +0200

    ACME adaptation

commit 1b763b91e7a03e426227129c7f22f0ce57a4c197
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 17:17:10 2020 +0200

    ACME adaptation

commit e92a4b57b232cd85eb1e71090b8a89c7c8461ebc
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 17:15:37 2020 +0200

    ACME adaptation

commit de3c693e8a7e73ea5289198946058e3240894e6a
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 17:10:05 2020 +0200

    ACME adaptation

commit f9bd7ae0f04e932d613be9ed5cb19af9be5d338e
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 13 14:34:44 2020 +0200

    ACME adaptation

commit 694dee52555dbfc2b1f7f452a9671ff51106c057
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 13 14:16:14 2020 +0200

    ACME adaptation

commit 0af2c55edfcd22942d9f25417eb0d35f55b71604
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 11 17:38:09 2020 +0200

    ACME adaptation

commit 2015e17334bd56a1e8a13a5abc098d9c2e7ea44f
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 11 16:46:05 2020 +0200

    ACME adaptation

commit b1e972162798d60f4483cd6cc261e856c20c2c8c
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 11 16:24:31 2020 +0200

    ACME adaptation

commit 9d027e868466901ba53bf074a79ec8cf16273021
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 11 15:04:31 2020 +0200

    ACME adaptation

commit 957186deddd1aa4f3b4f1aa1f421e4239a584e57
Author: FeralChild64 <you@example.com>
Date:   Thu Sep 10 22:49:07 2020 +0200

    ACME adaptation

commit b8060f67a455cfac109f08d96b62c360d693b931
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 23:07:28 2020 +0200

    ACME adaptation

commit e54d004568f44bbfe5c070ef1d7cf3544112e497
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 22:58:20 2020 +0200

    ACME adaptation

commit f90b77f073c5a605cb31c6ee451f65c8a8aff7d8
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 22:12:09 2020 +0200

    ACME adaptation

commit b211bb4afcd9c58fe1f5c92f3007717d611cd531
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 22:01:40 2020 +0200

    ACME adaptation

commit 8d7ea343b07e9e08e5f77f3c414758a6cffd0440
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 21:38:34 2020 +0200

    ACME adaptation

commit 46413eb0d92d6400aba0ff8dfe556e61e8a44d78
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 21:07:47 2020 +0200

    ACME adaptation

commit 9f98f69ecc21f7b74a5eb89e247f5a2c6fcb655d
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 20:05:03 2020 +0200

    ACME adaptation

commit 7bb9f1cadc682c7e0a4a6796739d860d473ca110
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 19:55:12 2020 +0200

    ACME adaptation

commit 5fc115392b5bdca6b56f67ad866b1884d2d2bdf8
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 19:31:10 2020 +0200

    ACME adaptation

commit b7940fc60e568d859df9e3156f6bacc6d685b2cc
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 19:16:09 2020 +0200

    ACME adaptation

commit 56288cb97197561afa0816b29c134ec1190e8eab
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 18:48:23 2020 +0200

    ACME adaptation

commit 10401a60fc7922a53d782120ef6795d889140218
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 16:34:16 2020 +0200

    ACME adaptation

commit 8ce76e4d2b56837a691ae84b1a412a2ae32a157b
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 16:20:44 2020 +0200

    ACME adaptation

commit 33fade899fa6172ea6b5b5f6683bb61f544429fd
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 15:28:46 2020 +0200

    ACME adaptation

commit a416f04734402fcfbc57a933731376df2e0180a1
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 12:40:03 2020 +0200

    ACME adaptation

commit f8daee005b1d29f6912723be2ac94bc5fbeb0508
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 7 23:29:54 2020 +0200

    ACME adaptation

commit 83fe6bdd0b08a44fdbfc6eefe323a4b194ccaf5b
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 7 22:23:16 2020 +0200

    ACME adaptation

commit cb1f75620b9c83000a15c9c7f7acefdfee79a979
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 7 19:23:12 2020 +0200

    ACME adaptation

commit e524d517c933ae1f0aeb49764d307fadb4845025
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 6 08:24:25 2020 +0200

    ACME adaptation - replaced comments

commit 2ab572c3a21f4a78a7312d0e684bc11d91d1717a
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 5 17:59:10 2020 +0200

    ACME adaptation - replaced the assembler
This commit is contained in:
FeralChild64 committed 2020-09-20 20:22:36 +02:00
1 parent bfc8291e41
commit c8d255130c
685 files changed
+15835 -16296
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/aliases/,aliases_cpu.s
+101 -509
View File
@@ -1,546 +1,138 @@
//
// Provide pseudocommands (and other goodies) to make CPU optimizations easier
//
#if CONFIG_CPU_WDC_65C02 || CONFIG_CPU_CSG_65CE02 || CONFIG_CPU_CSG_4510 || CONFIG_CPU_M65_45GS02 || CONFIG_CPU_WDC_65816
.cpu _65c02
#define HAS_OPCODES_65C02
#define HAS_BCD_SAFE_INTERRUPTS
#endif
#if CONFIG_CPU_CSG_65CE02 || CONFIG_CPU_CSG_4510 || CONFIG_CPU_M65_45GS02
#define HAS_OPCODES_65CE02
#endif
#if CONFIG_CPU_CSG_4510 || CONFIG_CPU_M65_45GS02
#define HAS_OPCODES_4510
#endif
#if CONFIG_CPU_M65_45GS02
#define HAS_OPCODES_45GS02
#endif
#if CONFIG_CPU_WDC_65816
#define HAS_OPCODES_65816
#endif
;
; Various macros - mainly for making CPU-specific optimizations easier
;
//
// These are not exactly for optimization - but to encourage proper usage of panic screen
//
.pseudocommand panic code
{
// If case no panic screen is used, we can skip providing error codes within Kernal
#if CONFIG_PANIC_SCREEN
lda code
#endif
!macro panic @code {
; If case no panic screen is used, we can skip providing error codes within Kernal
!ifdef CONFIG_PANIC_SCREEN { lda #@code }
jmp ($E4B7)
}
//
// Macros for generating jumptables
//
.macro put_jumptable_lo(list)
{
.for (var i = 0; i < list.size(); i++)
{
.byte mod((list.get(i) - 1), $100)
}
!macro skip_2_bytes_trash_nvz {
; Trick to skip a 2-byte instruction
!byte $2C
}
.macro put_jumptable_hi(list)
{
.for (var i = 0; i < list.size(); i++)
{
.byte floor((list.get(i) - 1) / $100)
}
}
#if HAS_OPCODES_65C02
.macro put_jumptable(list)
{
.for (var i = 0; i < list.size(); i++)
{
.word list.get(i)
}
}
#endif
//
// Trick to skip a 2-byte instruction
//
.pseudocommand skip_2_bytes_trash_nvz { .byte $2C }
//
// Memory mapping for C65 and MEGA65
//
#if HAS_OPCODES_4510
.pseudocommand map { .byte $5C }
.pseudocommand eom { .byte $EA }
#endif
//
// Some additional 65C02 instructions
//
#if HAS_OPCODES_65C02
.pseudocommand inc_a { .byte $1A }
.pseudocommand dec_a { .byte $3A }
#endif
//
// Some additional 65CE02 instructions
//
#if HAS_OPCODES_65CE02
// CPU flags support
.pseudocommand cle { .byte $02 }
.pseudocommand see { .byte $03 }
// .B register support
.pseudocommand tab { .byte $5B }
.pseudocommand tba { .byte $7B }
// .Z register support
.pseudocommand inz { .byte $1B }
.pseudocommand dez { .byte $3B }
.pseudocommand phz { .byte $DB }
.pseudocommand plz { .byte $FB }
.pseudocommand taz { .byte $4B }
.pseudocommand tza { .byte $6B }
// 16-bit data processing
.pseudocommand dew addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "DEW requires zeropage address"
.byte $C3, arg
}
.pseudocommand inw addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "INW requires zeropage address"
.byte $E3, arg
}
// Zero page bit handling
.pseudocommand rmb0 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "RMB0 requires zeropage address"
.byte $07, arg
}
.pseudocommand rmb1 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "RMB1 requires zeropage address"
.byte $17, arg
}
.pseudocommand rmb2 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "RMB2 requires zeropage address"
.byte $27, arg
}
.pseudocommand rmb3 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "RMB3 requires zeropage address"
.byte $37, arg
}
.pseudocommand rmb4 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "RMB4 requires zeropage address"
.byte $47, arg
}
.pseudocommand rmb5 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "RMB5 requires zeropage address"
.byte $57, arg
}
.pseudocommand rmb6 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "RMB6 requires zeropage address"
.byte $67, arg
}
.pseudocommand rmb7 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "RMB7 requires zeropage address"
.byte $77, arg
}
.pseudocommand smb0 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "SMB0 requires zeropage address"
.byte $87, arg
}
.pseudocommand smb1 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "SMB1 requires zeropage address"
.byte $97, arg
}
.pseudocommand smb2 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "SMB2 requires zeropage address"
.byte $A7, arg
}
.pseudocommand smb3 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "SMB3 requires zeropage address"
.byte $B7, arg
}
.pseudocommand smb4 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "SMB4 requires zeropage address"
.byte $C7, arg
}
.pseudocommand smb5 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "SMB5 requires zeropage address"
.byte $D7, arg
}
.pseudocommand smb6 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "SMB6 requires zeropage address"
.byte $E7, arg
}
.pseudocommand smb7 addr
{
.var arg = addr.getValue()
.if (arg > $FF) .error "SMB7 requires zeropage address"
.byte $F7, arg
}
// Additional addressing modes
.pseudocommand jsr_ind addr
{
.var arg = addr.getValue()
.byte $22, mod(arg, $100), floor(arg / $100)
}
.pseudocommand jsr_ind_x addr
{
.var arg = addr.getValue()
.byte $23, mod(arg, $100), floor(arg / $100)
}
// Others, taken from https://github.com/smnjameson/M65_KickAsm_PseudoCommands
.const z = -999 // allows (base page),z addressing mode
.const sy = -998 // allows (base page, s),y addressing mode
.const AT_IZEROPAGEZ = 13 // adds a pseudo addressing mode
.const AT_INDIRECTX = -5 // adds a pseudo addressing mode
.function GetAdressingModeType(arg) {
.if(arg == AT_NONE) .return "AT_NONE"
.if(arg == AT_IMMEDIATE) .return "AT_IMMEDIATE"
.if(arg == AT_INDIRECT) .return "AT_INDIRECT"
.if(arg == AT_INDIRECTX) .return "AT_INDIRECTX"
.if(arg == AT_ABSOLUTE) .return "AT_ABSOLUTE"
.if(arg == AT_ABSOLUTEX) .return "AT_ABSOLUTEX"
.if(arg == AT_ABSOLUTEY) .return "AT_ABSOLUTEY"
.if(arg == AT_IZEROPAGEX) .return "AT_IZEROPAGEX"
.if(arg == AT_IZEROPAGEY) .return "AT_IZEROPAGEY"
.if(arg == AT_IZEROPAGEZ) .return "AT_IZEROPAGEZ"
.return arg
}
.pseudocommand cpz arg {
.var value = arg.getValue()
.var type = arg.getType()
.if(type == AT_IMMEDIATE) {
.byte $C2, value
} else .if(type == AT_ABSOLUTE) {
.if(value <= $FF ) {
.byte $D4, value
} else {
.byte $DC, <value, >value
}
!macro lda_zero {
; WARNING: this one can be dangerous in soem cases, use with care!
!ifdef HAS_OPCODES_65CE02 {
tba
} else {
.error "Invalid adressingmode. 'cpz' doesn't support "+GetAdressingModeType(type)+" mode"
lda #$00
}
}
.pseudocommand lda arg {
.var value = arg.getValue()
.var type = arg.getType()
.if(type != AT_IZEROPAGEZ) .error "':lda' only accepts AT_IZEROPAGEZ"
.if(value > $FF ) .error "':lda ($nn),z' requires zeropage address"
.byte $B2, value
}
.pseudocommand ldz arg
{
.var value = arg.getValue()
.var type = arg.getType()
.if(type == AT_IMMEDIATE) {
.byte $A3, value
} else .if(type == AT_ABSOLUTE) {
.byte $AB, <value, >value
} else .if(type == AT_ABSOLUTEX) {
.byte $BB, <value, >value
; Stack manipulation - some CPUs will leave .A unchanged, some will use it as temporary storage, so consider .A trashed
!macro phx_trash_a { !ifdef HAS_OPCODES_65C02 {
phx
} else {
.error "Invalid adressingmode. 'ldz' doesn't support "+GetAdressingModeType(type)+" mode"
}
}
txa
pha
} }
.pseudocommand sta arg {
.var value = arg.getValue()
.var type = arg.getType()
.if(type != AT_IZEROPAGEZ) .error "':sta' only accepts AT_IZEROPAGEZ"
.if(value > $FF ) .error "':sta ($nn),z' requires zeropage address"
.byte $92, value
}
!macro phy_trash_a { !ifdef HAS_OPCODES_65C02 {
phy
} else {
tya
pha
} }
// Flat memory access support
!macro plx_trash_a { !ifdef HAS_OPCODES_65C02 {
plx
} else {
pla
tax
} }
.pseudocommand lda_lp arg {
.var value = arg.getValue()
.var type = arg.getType()
.if(type != AT_IZEROPAGEZ) .error "'lda_lp' only accepts AT_IZEROPAGEZ"
.if(value > $FF ) .error "'lda_lp' requires zeropage address"
nop
.byte $B2, value
}
.pseudocommand sta_lp arg {
.var value = arg.getValue()
.var type = arg.getType()
.if(type != AT_IZEROPAGEZ) .error "'sta_lp' only accepts AT_IZEROPAGEZ"
.if(value > $FF ) .error "'sta_lp' requires zeropage address"
nop
.byte $92, value
}
#endif
!macro ply_trash_a { !ifdef HAS_OPCODES_65C02 {
ply
} else {
pla
tay
} }
//
// Calculation shortcuts
//
; Near jump, on some CPUs can be substituted with shorter instruction
.pseudocommand lda_zero // WARNING: do not use within interrupts
{
#if HAS_OPCODES_65CE02
tba
#else
lda #$00
#endif
}
!macro bra @dst { !ifdef HAS_OPCODE_BRA {
bra @dst
} else {
jmp @dst
} }
//
// Stack manipulation - some CPUs will leave .A unchanged, some will use it as temporary storage, so consider .A trashed
//
; NOP definition, MEGA65 CPU uses EOM instead
.pseudocommand phx_trash_a
{
#if HAS_OPCODES_65C02
phx
#else
txa
pha
#endif
}
.pseudocommand phy_trash_a
{
#if HAS_OPCODES_65C02
phy
#else
tya
pha
#endif
}
.pseudocommand plx_trash_a
{
#if HAS_OPCODES_65C02
plx
#else
pla
tax
#endif
}
.pseudocommand ply_trash_a
{
#if HAS_OPCODES_65C02
ply
#else
pla
tay
#endif
}
!macro nop { !ifdef CONFIG_MB_M65 {
eom
} else {
nop
} }
//
// Branches with far offsets, substitutes by Bxx + JMP for CPUs not supporting the instruction
//
; Branches with far offsets, substitutes by Bxx + JMP for CPUs not supporting the instruction
.pseudocommand bcs_16 dst
{
#if HAS_OPCODES_65CE02
.var offset = mod($10000 + dst.getValue() - *, $10000) -2
.byte $B3, mod(offset, $100), floor(offset / $100)
#else
bcc __l
jmp dst
__l:
#endif
}
!macro bcs @dst { !ifdef HAS_OPCODES_65CE02 {
lbcs @dst
} else {
bcc *+5
jmp @dst
} }
.pseudocommand bcc_16 dst
{
#if HAS_OPCODES_65CE02
.var offset = mod($10000 + dst.getValue() - *, $10000) -2
.byte $93, mod(offset, $100), floor(offset / $100)
#else
bcs __l
jmp dst
__l:
#endif
}
!macro bcc @dst { !ifdef HAS_OPCODES_65CE02 {
lbcc @dst
} else {
bcs *+5
jmp @dst
} }
.pseudocommand beq_16 dst
{
#if HAS_OPCODES_65CE02
.var offset = mod($10000 + dst.getValue() - *, $10000) -2
.byte $F3, mod(offset, $100), floor(offset / $100)
#else
bne __l
jmp dst
__l:
#endif
}
!macro beq @dst { !ifdef HAS_OPCODES_65CE02 {
lbeq @dst
} else {
bne *+5
jmp @dst
} }
.pseudocommand bne_16 dst
{
#if HAS_OPCODES_65CE02
.var offset = mod($10000 + dst.getValue() - *, $10000) -2
.byte $D3, mod(offset, $100), floor(offset / $100)
#else
beq __l
jmp dst
__l:
#endif
}
!macro bne @dst { !ifdef HAS_OPCODES_65CE02 {
lbne @dst
} else {
beq *+5
jmp @dst
} }
.pseudocommand bmi_16 dst
{
#if HAS_OPCODES_65CE02
.var offset = mod($10000 + dst.getValue() - *, $10000) -2
.byte $33, mod(offset, $100), floor(offset / $100)
#else
bpl __l
jmp dst
__l:
#endif
}
!macro bmi @dst { !ifdef HAS_OPCODES_65CE02 {
lbmi @dst
} else {
bpl *+5
jmp @dst
} }
.pseudocommand bpl_16 dst
{
#if HAS_OPCODES_65CE02
.var offset = mod($10000 + dst.getValue() - *, $10000) -2
.byte $13, mod(offset, $100), floor(offset / $100)
#else
bmi __l
jmp dst
__l:
#endif
}
!macro bpl @dst { !ifdef HAS_OPCODES_65CE02 {
lbpl @dst
} else {
bmi *+5
jmp @dst
} }
.pseudocommand bvc_16 dst
{
#if HAS_OPCODES_65CE02
.var offset = mod($10000 + dst.getValue() - *, $10000) -2
.byte $53, mod(offset, $100), floor(offset / $100)
#else
bvs __l
jmp dst
__l:
#endif
}
!macro bvc @dst { !ifdef HAS_OPCODES_65CE02 {
lbvc @dst
} else {
bvs *+5
jmp @dst
} }
.pseudocommand bvs_16 dst
{
#if HAS_OPCODES_65CE02
.var offset = mod($10000 + dst.getValue() - *, $10000) -2
.byte $73, mod(offset, $100), floor(offset / $100)
#else
bvc __l
jmp dst
__l:
#endif
}
//
// Near jump, on some CPUs can be substituted with shorter instruction
//
.pseudocommand jmp_8 dst
{
#if HAS_OPCODES_65C02
bra dst
#else
jmp dst
#endif
}
!macro bvs @dst { !ifdef HAS_OPCODES_65CE02 {
lbvs @dst
} else {
bvc *+5
jmp @dst
} }