chris/open-roms
1
0 Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

migrated to ACME assembler

Browse Source 
commit 145d64aa6e78838ed07cefed372f0ad6a4687e97
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 20:16:57 2020 +0200

    ACME adaptation

commit 885209d7822286744ea53232ae7461472a01d5d6
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 19:57:25 2020 +0200

    ACME adaptation

commit 334d84486bc603551887e7cbeb59d329f2224cc7
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 18:29:15 2020 +0200

    ACME adaptation

commit b5966f49bcd8f0ca79cbec93819a31238924707e
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 18:09:31 2020 +0200

    ACME adaptation

commit 786536a93a5eab5e676fca99625b4eb094a554e7
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 17:24:48 2020 +0200

    ACME adaptation

commit 704c70dfb1f5d68775d6f3da220803b8a3990f56
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 15:07:12 2020 +0200

    ACME adaptation

commit 136874964c9083b375f151475310f9636871fc72
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 14:45:14 2020 +0200

    ACME adaptation

commit 8eca0d5700b72d04336e72c5cd3a68e18b85f96d
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 14:06:52 2020 +0200

    ACME adaptation

commit 11d29eb7ee318239d782f85498b6d0524624d5c4
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 13:56:45 2020 +0200

    ACME apaptation

commit c9b5e5e04cceb92c66bc027e6440bc0f7c5a499f
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 13:49:04 2020 +0200

    ACME adaptation

commit f5cc254cbc921f07863807468cb3fe26b410b409
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 20 13:01:18 2020 +0200

    ACME adaptation

commit e135a27bf9c30cc0965379c954564e06406303b1
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 19 21:55:01 2020 +0200

    ACME adaptation

commit e9dfddf90d9e2795e88b7da40ae050d733faeb56
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 19 21:48:47 2020 +0200

    Makefile fix

commit 07030104c65cf5e5beeacf6d629ccb9245e58657
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 19 21:42:00 2020 +0200

    ACME adaptation

commit f824362ee5bcfbffca86c430b57773b2ffd65655
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 19 20:14:56 2020 +0200

    ACME adaptation

commit 3a3c59007dcd4940d89b8669f34ca56b61c25fdf
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 18 21:51:45 2020 +0200

    ACME adaptation

commit 6790ef7bc88a41de2881c69b7524dd4ab8c74b5d
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 18 20:35:23 2020 +0200

    ACME adaptation

commit 38ad18b90e9ec713aa7ca49576b3388ce1733357
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 18 18:46:20 2020 +0200

    ACME adaptation

commit 541340371122a9702f7b2d9771c298223cffd0e9
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 18 16:49:46 2020 +0200

    ACME adaptation

commit 25cfd5e186459be1a260d3eb8cfff767838de370
Author: FeralChild64 <you@example.com>
Date:   Thu Sep 17 20:13:33 2020 +0200

    ACME adaptation

commit f61599444d5b1d03d8fd8e4a6a7c3b85069bedb3
Author: FeralChild64 <you@example.com>
Date:   Thu Sep 17 19:29:23 2020 +0200

    ACME adaptation

commit b290be31ec7bb2e5723607697da1bbc621c84429
Author: FeralChild64 <you@example.com>
Date:   Thu Sep 17 17:20:14 2020 +0200

    ACME adaptation

commit 877be9e856880d98fd4bcb25b42aaaacda9dc463
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 16 21:47:38 2020 +0200

    ACME adaptation

commit bb20edaf85d386e41d5c2f715b745b68fbd3362e
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 16 21:31:30 2020 +0200

    ACME adaptation

commit c5d31bd8685abce37c8e254d15aac20bd1570d9f
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 16 18:40:49 2020 +0200

    ACME adaptation

commit 29349826b38f8a89649171559dc8cf24c560aff1
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 23:35:47 2020 +0200

    ACME adaptation

commit 8bcd6a621c4b11766d0cf34f79858ba90a67248e
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 22:52:25 2020 +0200

    ACME adaptation

commit e87a69edc2ce4bfcc460c31e08dcc352a985f88d
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 22:43:27 2020 +0200

    ACME adaptation

commit f49a097bd52e96d00b866c02bda7121e4543233c
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 19:02:07 2020 +0200

    ACME adaptation

commit fa0e9214a633b8e8f867cc70925b390940dcd426
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 17:47:19 2020 +0200

    ACME adaptation

commit 1b763b91e7a03e426227129c7f22f0ce57a4c197
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 17:17:10 2020 +0200

    ACME adaptation

commit e92a4b57b232cd85eb1e71090b8a89c7c8461ebc
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 17:15:37 2020 +0200

    ACME adaptation

commit de3c693e8a7e73ea5289198946058e3240894e6a
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 14 17:10:05 2020 +0200

    ACME adaptation

commit f9bd7ae0f04e932d613be9ed5cb19af9be5d338e
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 13 14:34:44 2020 +0200

    ACME adaptation

commit 694dee52555dbfc2b1f7f452a9671ff51106c057
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 13 14:16:14 2020 +0200

    ACME adaptation

commit 0af2c55edfcd22942d9f25417eb0d35f55b71604
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 11 17:38:09 2020 +0200

    ACME adaptation

commit 2015e17334bd56a1e8a13a5abc098d9c2e7ea44f
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 11 16:46:05 2020 +0200

    ACME adaptation

commit b1e972162798d60f4483cd6cc261e856c20c2c8c
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 11 16:24:31 2020 +0200

    ACME adaptation

commit 9d027e868466901ba53bf074a79ec8cf16273021
Author: FeralChild64 <you@example.com>
Date:   Fri Sep 11 15:04:31 2020 +0200

    ACME adaptation

commit 957186deddd1aa4f3b4f1aa1f421e4239a584e57
Author: FeralChild64 <you@example.com>
Date:   Thu Sep 10 22:49:07 2020 +0200

    ACME adaptation

commit b8060f67a455cfac109f08d96b62c360d693b931
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 23:07:28 2020 +0200

    ACME adaptation

commit e54d004568f44bbfe5c070ef1d7cf3544112e497
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 22:58:20 2020 +0200

    ACME adaptation

commit f90b77f073c5a605cb31c6ee451f65c8a8aff7d8
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 22:12:09 2020 +0200

    ACME adaptation

commit b211bb4afcd9c58fe1f5c92f3007717d611cd531
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 22:01:40 2020 +0200

    ACME adaptation

commit 8d7ea343b07e9e08e5f77f3c414758a6cffd0440
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 21:38:34 2020 +0200

    ACME adaptation

commit 46413eb0d92d6400aba0ff8dfe556e61e8a44d78
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 21:07:47 2020 +0200

    ACME adaptation

commit 9f98f69ecc21f7b74a5eb89e247f5a2c6fcb655d
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 20:05:03 2020 +0200

    ACME adaptation

commit 7bb9f1cadc682c7e0a4a6796739d860d473ca110
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 19:55:12 2020 +0200

    ACME adaptation

commit 5fc115392b5bdca6b56f67ad866b1884d2d2bdf8
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 19:31:10 2020 +0200

    ACME adaptation

commit b7940fc60e568d859df9e3156f6bacc6d685b2cc
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 19:16:09 2020 +0200

    ACME adaptation

commit 56288cb97197561afa0816b29c134ec1190e8eab
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 18:48:23 2020 +0200

    ACME adaptation

commit 10401a60fc7922a53d782120ef6795d889140218
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 16:34:16 2020 +0200

    ACME adaptation

commit 8ce76e4d2b56837a691ae84b1a412a2ae32a157b
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 16:20:44 2020 +0200

    ACME adaptation

commit 33fade899fa6172ea6b5b5f6683bb61f544429fd
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 15:28:46 2020 +0200

    ACME adaptation

commit a416f04734402fcfbc57a933731376df2e0180a1
Author: FeralChild64 <you@example.com>
Date:   Wed Sep 9 12:40:03 2020 +0200

    ACME adaptation

commit f8daee005b1d29f6912723be2ac94bc5fbeb0508
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 7 23:29:54 2020 +0200

    ACME adaptation

commit 83fe6bdd0b08a44fdbfc6eefe323a4b194ccaf5b
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 7 22:23:16 2020 +0200

    ACME adaptation

commit cb1f75620b9c83000a15c9c7f7acefdfee79a979
Author: FeralChild64 <you@example.com>
Date:   Mon Sep 7 19:23:12 2020 +0200

    ACME adaptation

commit e524d517c933ae1f0aeb49764d307fadb4845025
Author: FeralChild64 <you@example.com>
Date:   Sun Sep 6 08:24:25 2020 +0200

    ACME adaptation - replaced comments

commit 2ab572c3a21f4a78a7312d0e684bc11d91d1717a
Author: FeralChild64 <you@example.com>
Date:   Sat Sep 5 17:59:10 2020 +0200

    ACME adaptation - replaced the assembler
This commit is contained in:
FeralChild64 committed 2020-09-20 20:22:36 +02:00
1 parent bfc8291e41
commit c8d255130c
685 files changed
+15835 -16296
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/kernal/iec_fast/burst_cia1_advertise.s
+18 -20
View File
@@ -1,36 +1,34 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// Advertise burst IEC protocol support to the receiver
//
;
; Advertise burst IEC protocol support to the receiver
;
//
// Based on idea by Pasi 'Albert' Ojala and description from
// https://sites.google.com/site/h2obsession/CBM/C128/fast-serial-for-uiec
//
;
; Based on idea by Pasi 'Albert' Ojala and description from
; https://sites.google.com/site/h2obsession/CBM/C128/fast-serial-for-uiec
;
#if CONFIG_IEC_BURST_CIA1
!ifdef CONFIG_IEC_BURST_CIA1 {
burst_advertise:
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
// Skip if other protocol (only JiffyDOS is possible at this moment) already detected
; Skip if other protocol (only JiffyDOS is possible at this moment) already detected
lda IECPROTO
bmi !+
bmi @1
bne burst_advertise_done
!:
#endif
@1:
}
panic #$FF // XXX implement this
+panic #$FF ; XXX implement this
burst_advertise_done:
rts
#endif
}
src/kernal/iec_fast/burst_cia2_advertise.s
+29 -31
View File
@@ -1,60 +1,58 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// Advertise burst IEC protocol support to the receiver
//
;
; Advertise burst IEC protocol support to the receiver
;
//
// Based on idea by Pasi 'Albert' Ojala and description from
// https://sites.google.com/site/h2obsession/CBM/C128/fast-serial-for-uiec
//
;
; Based on idea by Pasi 'Albert' Ojala and description from
; https://sites.google.com/site/h2obsession/CBM/C128/fast-serial-for-uiec
;
#if CONFIG_IEC_BURST_CIA2
!ifdef CONFIG_IEC_BURST_CIA2 {
burst_advertise:
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
// Skip if other protocol (only JiffyDOS is possible at this moment) already detected
; Skip if other protocol (only JiffyDOS is possible at this moment) already detected
lda IECPROTO
bmi !+
bmi @1
bne burst_advertise_done
!:
#endif
@1:
}
// Make sure this is not done under ATN
; Make sure this is not done under ATN
jst iec_release_atn
// Set the clock rate to the fastest possible
; Set the clock rate to the fastest possible
ldy #$01
sty CIA2_TIMALO
dey
sty CIA2_TIMAHI
// Prepare registers for transfer
; Prepare registers for transfer
lda #$C1
sta CIA2_CRA // start timer A, serial out, TOD 50Hz
bit CIA2_ICR // clear interrupt register
sta CIA2_CRA ; start timer A, serial out, TOD 50Hz
bit CIA2_ICR ; clear interrupt register
// Send test byte
lda #$FF // $FF keeps DATA released, see https://www.c64-wiki.com/wiki/Fast_serial_bus_protocol
; Send test byte
lda #$FF ; $FF keeps DATA released, see https://www.c64-wiki.com/wiki/Fast_serial_bus_protocol
sta CIA2_SDR
// Wait until byte sent
lda #$08 // interrupt mask
!:
; Wait until byte sent
lda #$08 ; interrupt mask
@2:
bit CIA2_ICR
beq !-
beq @2
// FALLTROUGH
; FALLTROUGH
burst_advertise_done:
rts
#endif
}
src/kernal/iec_fast/burst_m65_advertise.s
+14 -16
View File
@@ -1,31 +1,29 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// Advertise burst IEC protocol support to the receiver
//
;
; Advertise burst IEC protocol support to the receiver
;
#if CONFIG_IEC_BURST_MEGA_65
!ifdef CONFIG_IEC_BURST_M65 {
burst_advertise:
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
// Skip if other protocol (only JiffyDOS is possible at this moment) already detected
; Skip if other protocol (only JiffyDOS is possible at this moment) already detected
lda IECPROTO
bmi !+
bmi @1
bne burst_advertise_done:
!:
#endif
@1:
}
panic #$FF // XXX implement this
+panic #$FF ; XXX implement this
burst_advertise_done:
rts
#endif
}
src/kernal/iec_fast/dolphindos_detect.s
+26 -26
View File
@@ -1,38 +1,38 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// Helper routine for JiffyDOS detection
//
;
; Helper routine for JiffyDOS detection
;
// The standard parallel cable (used by SpeedDOS, DolphinDOS 2, etc.) connects the following UserPort lines:
// - PB0-PB7 - CIA2_PRB ($DD01), CIA #2 port B
// - PC2, FLAG2 - CIA2_ICR ($DD0D), CIA #2 handshaking line
//
// See:
// - http://sta.c64.org/cbmpar41c.html
// - http://sta.c64.org/cbmpar71c.html
// - Commodore 64 Programers Referencee Guide, pages 360-361, 429
// - Computes Mapping the C64, page 183
; The standard parallel cable (used by SpeedDOS, DolphinDOS 2, etc.) connects the following UserPort lines:
; - PB0-PB7 - CIA2_PRB ($DD01), CIA #2 port B
; - PC2, FLAG2 - CIA2_ICR ($DD0D), CIA #2 handshaking line
;
; See:
; - http://sta.c64.org/cbmpar41c.html
; - http://sta.c64.org/cbmpar71c.html
; - Commodore 64 Programers Referencee Guide, pages 360-361, 429
; - Computes Mapping the C64, page 183
#if CONFIG_IEC_DOLPHINDOS
!ifdef CONFIG_IEC_DOLPHINDOS {
dolphindos_detect:
// Make sure the port settings are correct
; Make sure the port settings are correct
lda #$7F
sta CIA2_ICR // disable interrupt generation
sta CIA2_ICR ; disable interrupt generation
lda #$00
sta CIA2_DDRB // set all port B lines as input
sta CIA2_DDRB ; set all port B lines as input
// According to logs collected from modified VICE emulator, original DolphinDOS ROM
// constantly reads $DD0D and $DD01 until handshake bit of $DD0D is set, or some kind
// of timeout occurs
; According to logs collected from modified VICE emulator, original DolphinDOS ROM
; constantly reads $DD0D and $DD01 until handshake bit of $DD0D is set, or some kind
; of timeout occurs
ldx #$20
@@ -41,12 +41,12 @@ dolphindos_detect_loop:
lda CIA2_ICR
cmp #$10
beq dolphindos_detect_success
lda CIA2_PRB // XXX do we need this read?
lda CIA2_PRB ; XXX do we need this read?
dex
bne dolphindos_detect_loop
// FALLTROUGH - protocol not detected
; FALLTROUGH - protocol not detected
dolphindos_detect_fail:
@@ -54,7 +54,7 @@ dolphindos_detect_fail:
dolphindos_detect_success:
// Protocol detected
; Protocol detected
lda #IEC_DOLPHIN
sta IECPROTO
@@ -62,4 +62,4 @@ dolphindos_detect_success:
rts
#endif // CONFIG_IEC_DOLPHINDOS
} ; CONFIG_IEC_DOLPHINDOS
src/kernal/iec_fast/dolphindos_load.s
+50 -51
View File
@@ -1,122 +1,121 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// DolphinDOS protocol support for IEC - optimized load loop
//
;
; DolphinDOS protocol support for IEC - optimized load loop
;
#if CONFIG_IEC_DOLPHINDOS && !CONFIG_MEMORY_MODEL_60K
!ifdef CONFIG_IEC_DOLPHINDOS { !ifndef CONFIG_MEMORY_MODEL_60K {
dolphindos_load:
// Timing is critical for some parts, do not allow interrupts
; Timing is critical for some parts, do not allow interrupts
sei
// A trick to shorten EAL update time
; A trick to shorten EAL update time
ldy #$00
#if CONFIG_IEC_DOLPHINDOS_FAST
// Another trick: prepare values for quickly setting/releasing DATA
!ifdef CONFIG_IEC_DOLPHINDOS_FAST {
; Another trick: prepare values for quickly setting/releasing DATA
lda CIA2_PRA
and #$FF - BIT_CIA2_PRA_DAT_OUT - BIT_CIA2_PRA_CLK_OUT - BIT_CIA2_PRA_ATN_OUT
sta IECPROTO // release DATA
sta IECPROTO ; release DATA
ora #BIT_CIA2_PRA_DAT_OUT
sta TBTCNT // pull DATA
#endif
// FALLTROUGH
sta TBTCNT ; pull DATA
}
; FALLTROUGH
dolphindos_load_loop:
#if !CONFIG_IEC_DOLPHINDOS_FAST
// Check if this was EOI
!ifndef CONFIG_IEC_DOLPHINDOS_FAST {
; Check if this was EOI
bit IOSTATUS
bvs dolphindos_load_end
#endif
}
// Wait for the talker to release the CLK line
!:
; Wait for the talker to release the CLK line
@1:
bit CIA2_PRA
bvc !-
bvc @1
// Release the DATA to signal we are ready
#if !CONFIG_IEC_DOLPHINDOS_FAST
; Release the DATA to signal we are ready
!ifndef CONFIG_IEC_DOLPHINDOS_FAST {
lda CIA2_PRA
and #$FF - BIT_CIA2_PRA_DAT_OUT // release
#else
and #$FF - BIT_CIA2_PRA_DAT_OUT ; release
} else {
lda IECPROTO
#endif
}
sta CIA2_PRA
#if !CONFIG_IEC_DOLPHINDOS_FAST
!ifndef CONFIG_IEC_DOLPHINDOS_FAST {
// Check if EOI
jsr iec_rx_check_eoi // can damage .X, but this is safe
; Check if EOI
jsr iec_rx_check_eoi ; can damage .X, but this is safe
#else
} else {
// Check if EOI - inlined code to avoid wasting cycles on RTS
; Check if EOI - inlined code to avoid wasting cycles on RTS
ldx #$13
!:
@2:
bit CIA2_PRA
bvc dolphindos_load_no_eoi
dex
bne !-
bne @2
// EOI - mark it and retrieve the last byte
; EOI - mark it and retrieve the last byte
jsr iec_rx_check_eoi_confirm
lda CIA2_PRB
sta (EAL),y
// Update EAL for the last time
; Update EAL for the last time
sec
jsr iec_update_EAL_by_Y
// Restore proper IECPROTO value
; Restore proper IECPROTO value
lda #IEC_DOLPHIN
sta IECPROTO
// End of load loop
; End of load loop
jmp load_iec_loop_end
dolphindos_load_no_eoi:
#endif
}
// Retrieve and store byte
; Retrieve and store byte
lda CIA2_PRB
sta (EAL),y
// Pull DATA to acknowledge
#if !CONFIG_IEC_DOLPHINDOS_FAST
; Pull DATA to acknowledge
!ifndef CONFIG_IEC_DOLPHINDOS_FAST {
lda CIA2_PRA
ora #BIT_CIA2_PRA_DAT_OUT
#else
} else {
lda TBTCNT
#endif
}
sta CIA2_PRA
// Handle EAL
; Handle EAL
iny
bne dolphindos_load_loop
inc EAL+1
jmp dolphindos_load_loop
#if !CONFIG_IEC_DOLPHINDOS_FAST
!ifndef CONFIG_IEC_DOLPHINDOS_FAST {
dolphindos_load_end:
// Update EAL
; Update EAL
clc
jsr iec_update_EAL_by_Y
// End of load loop
; End of load loop
jmp load_iec_loop_end
#endif
}
#endif // CONFIG_IEC_DOLPHINDOS and not CONFIG_MEMORY_MODEL_60K
} } ; CONFIG_IEC_DOLPHINDOS and not CONFIG_MEMORY_MODEL_60K
src/kernal/iec_fast/jiffydos_bittable.s
+31 -32
View File
@@ -1,42 +1,41 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// Helper table for encoding lower nibble for JiffyDOS,
// values found by observing the actual transfer using
// original ROMs
//
;
; Helper table for encoding lower nibble for JiffyDOS,
; values found by observing the actual transfer using
; original ROMs
;
// Similar tables are probably used by nearly all the disk turbo loaders,
// either on the C64 or drive side, soometimes generated in RAM on the fly;
// example disk turbo presented below has a very similar table - but the
// values are in reversed order:
// - https://www.pagetable.com/?p=568
; Similar tables are probably used by nearly all the disk turbo loaders,
; either on the C64 or drive side, soometimes generated in RAM on the fly;
; example disk turbo presented below has a very similar table - but the
; values are in reversed order:
; - https://www.pagetable.com/?p=568
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
jiffydos_bittable:
.byte $00
.byte $80 // $10 + $70
.byte $20
.byte $A0 // $30 + $70
.byte $40
.byte $C0 // $50 + $70
.byte $60
.byte $E0 // $70 + $70
!byte $00
!byte $80 ; $10 + $70
!byte $20
!byte $A0 ; $30 + $70
!byte $40
!byte $C0 ; $50 + $70
!byte $60
!byte $E0 ; $70 + $70
.byte $10 // $80 - $70
.byte $90
.byte $30 // $A0 - $70
.byte $B0
.byte $50 // $C0 - $70
.byte $D0
.byte $70 // $E0 - $70
.byte $F0
!byte $10 ; $80 - $70
!byte $90
!byte $30 ; $A0 - $70
!byte $B0
!byte $50 ; $C0 - $70
!byte $D0
!byte $70 ; $E0 - $70
!byte $F0
#endif // CONFIG_IEC_JIFFYDOS
} ; CONFIG_IEC_JIFFYDOS
src/kernal/iec_fast/jiffydos_detect.s
+29 -31
View File
@@ -1,54 +1,52 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// Helper routine for JiffyDOS detection
//
;
; Helper routine for JiffyDOS detection
;
// Detection is done by inserting a long delay (above 400us?) during sending command last bit, see:
// - https://sites.google.com/site/h2obsession/CBM/C128/JiffySoft128
// - https://github.com/rkrajnc/sd2iec/blob/master/src/iec.c
// The 'iec.s' suggests, that the drive should respond by pulling data
; Detection is done by inserting a long delay (above 400us?) during sending command last bit, see:
; - https://sites.google.com/site/h2obsession/CBM/C128/JiffySoft128
; - https://github.com/rkrajnc/sd2iec/blob/master/src/iec.c
; The 'iec.s' suggests, that the drive should respond by pulling data
// The original JiffyDOS ROM seems to perform detection with every command
// (even though for many of them it always fails) and we have to replicate
// this behaviour for compatibility with at least 1541 JiffyDOS ROM
; The original JiffyDOS ROM seems to perform detection with every command
; (even though for many of them it always fails) and we have to replicate
; this behaviour for compatibility with at least 1541 JiffyDOS ROM
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
jiffydos_detect:
ldy #$25 // 400us is nearly 410 cycles on NTSC
// loop iteration below is 11 cycles,
// and several cycles were already used
ldy #$25 ; 400us is nearly 410 cycles on NTSC
; loop iteration below is 11 cycles,
; and several cycles were already used
jiffydos_detect_loop:
lda CIA2_PRA // 4 cycles
bpl jiffydos_detected // 2 cycles
dey // 2 cycles
bne jiffydos_detect_loop // 3 cycles if branch
lda CIA2_PRA ; 4 cycles
bpl jiffydos_detected ; 2 cycles
dey ; 2 cycles
bne jiffydos_detect_loop ; 3 cycles if branch
lda IECPROTO
bpl jiffydos_detect_end // no detection requested, preserve existing protocol
bpl jiffydos_detect_end ; no detection requested, preserve existing protocol
lda #IEC_NORMAL // normal protocol
beq jiffydos_store_proto // branch always
lda #IEC_NORMAL ; normal protocol
beq jiffydos_store_proto ; branch always
jiffydos_detected:
jsr iec_wait_for_data_release // guessed from VICE logs
lda #IEC_JIFFY // JiffyDOS protocol
jsr iec_wait_for_data_release ; guessed from VICE logs
lda #IEC_JIFFY ; JiffyDOS protocol
// FALLTROUGH
; FALLTROUGH
jiffydos_store_proto:
sta IECPROTO
// FALLTROUGH
; FALLTROUGH
jiffydos_detect_end:
rts
#endif // CONFIG_IEC_JIFFYDOS
}
src/kernal/iec_fast/jiffydos_load.s
+71 -74
View File
@@ -1,131 +1,129 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// JiffyDOS protocol support for IEC - optimized load loop
//
;
; JiffyDOS protocol support for IEC - optimized load loop
;
#if CONFIG_IEC_JIFFYDOS && !CONFIG_MEMORY_MODEL_60K
!ifdef CONFIG_IEC_JIFFYDOS { !ifndef CONFIG_MEMORY_MODEL_60K {
// Note: original JiffyDOS LOAD loop checks for RUN/STOP key every time a sector is read,
// see description at https://sites.google.com/site/h2obsession/CBM/C128/JiffySoft128
//
// For simplicity and some space savings, our routine does not check the RUN/STOP key at all;
// the protocol is fast enough (especially with modern flash mediums) that probably nobody
// will want to terminate the loading.
; Note: original JiffyDOS LOAD loop checks for RUN/STOP key every time a sector is read,
; see description at https://sites.google.com/site/h2obsession/CBM/C128/JiffySoft128
;
; For simplicity and some space savings, our routine does not check the RUN/STOP key at all;
; the protocol is fast enough (especially with modern flash mediums) that probably nobody
; will want to terminate the loading.
jiffydos_load:
// XXX implement JiffyDOS optimized LOAD protocol, this one is ineffective
; XXX implement JiffyDOS optimized LOAD protocol, this one is ineffective
// Timing is critical, do not allow interrupts
; Timing is critical, do not allow interrupts
sei
#if CONFIG_IEC_JIFFYDOS_BLANK
!ifdef CONFIG_IEC_JIFFYDOS_BLANK {
// Preserve register with screen status (blank/visible)
; Preserve register with screen status (blank/visible)
lda VIC_SCROLY
sta TBTCNT
// Blank screen to make sure no sprite/badline will interrupt
; Blank screen to make sure no sprite/badline will interrupt
jsr screen_off
// Preserve 3 lowest bits of CIA2_PRA XXX deduplicate this
; Preserve 3 lowest bits of CIA2_PRA XXX deduplicate this
lda CIA2_PRA
and #%00000111
sta C3PO
#else
} else {
// Store previous sprite status in temporary variable
; Store previous sprite status in temporary variable
jsr jiffydos_prepare
sta TBTCNT
}
#endif
// A trick to shorten EAL update time
; A trick to shorten EAL update time
ldy #$FF
// FALLTROUGH
; FALLTROUGH
jiffydos_load_loop:
// Wait until device is ready to send (releases CLK)
; Wait until device is ready to send (releases CLK)
jsr iec_wait_for_clk_release
// Prepare 'start sending' message
; Prepare 'start sending' message
lda CIA2_PRA
and #$FF - BIT_CIA2_PRA_DAT_OUT // release
and #$FF - BIT_CIA2_PRA_DAT_OUT ; release
#if CONFIG_IEC_JIFFYDOS_BLANK
!ifdef CONFIG_IEC_JIFFYDOS_BLANK {
// It seems JiffyDOS needs some time here; waste few cycles
nop
; It seems JiffyDOS needs some time here; waste few cycles
+nop
jsr iec_wait_rts
// Ask device to start sending bits
; Ask device to start sending bits
sta CIA2_PRA
#else
} else {
// Wait for appropriate moment, ask device to start sending bits
; Wait for appropriate moment, ask device to start sending bits
tax
jsr jiffydos_wait_line
stx CIA2_PRA // cycles: 4
stx CIA2_PRA ; cycles: 4
}
#endif
// Prepare 'data pull' byte, cycles: 3 + 2 + 2 = 7
; Prepare 'data pull' byte, cycles: 3 + 2 + 2 = 7
lda C3PO
ora #BIT_CIA2_PRA_DAT_OUT // pull
ora #BIT_CIA2_PRA_DAT_OUT ; pull
tax
// Delay, JiffyDOS needs some time, 4 cycles
nop
nop
; Delay, JiffyDOS needs some time, 4 cycles
+nop
+nop
// Get bits, cycles: 4 + 2 + 2 = 8
lda CIA2_PRA // bits 0 and 1 on CLK/DATA
; Get bits, cycles: 4 + 2 + 2 = 8
lda CIA2_PRA ; bits 0 and 1 on CLK/DATA
lsr
lsr
// Delay, JiffyDOS needs some time, 2 cycles
nop
; Delay, JiffyDOS needs some time, 2 cycles
+nop
// Get bits, cycles: 4 + 2 + 2 = 8
ora CIA2_PRA // bits 2 and 3 on CLK/DATA
; Get bits, cycles: 4 + 2 + 2 = 8
ora CIA2_PRA ; bits 2 and 3 on CLK/DATA
lsr
lsr
// Get bits, cycles: 3 + 4 + 2 + 2 = 11
; Get bits, cycles: 3 + 4 + 2 + 2 = 11
eor C3PO
eor CIA2_PRA // bits 4 and 5 on CLK/DATA
eor CIA2_PRA ; bits 4 and 5 on CLK/DATA
lsr
lsr
// Get bits, cycles: 3 + 4 = 7
; Get bits, cycles: 3 + 4 = 7
eor C3PO
eor CIA2_PRA // bits 6 and 7 on CLK/DATA
eor CIA2_PRA ; bits 6 and 7 on CLK/DATA
// Store retrieved byte, cycles: 2 + 6 = 8
iny // NTSC needs this delay
sta (EAL),y // not compatible with CONFIG_MEMORY_MODEL_60K
; Store retrieved byte, cycles: 2 + 6 = 8
iny ; NTSC needs this delay
sta (EAL),y ; not compatible with CONFIG_MEMORY_MODEL_60K
// Retrieve status bits, cycles: 4
; Retrieve status bits, cycles: 4
bit CIA2_PRA
// Pull DATA at the end, cycles: 4
; Pull DATA at the end, cycles: 4
stx CIA2_PRA
// If CLK line not active - this was the last byte
; If CLK line not active - this was the last byte
bvs jiffydos_load_end
// Handle EAL
; Handle EAL
cpy #$FF
bne jiffydos_load_loop
inc EAL+1
@@ -133,43 +131,42 @@ jiffydos_load_loop:
jiffydos_load_end:
// Save last byte
; Save last byte
tax
// Update EAL
; Update EAL
sec
jsr iec_update_EAL_by_Y
// Indicate that no byte waits in output buffer
; Indicate that no byte waits in output buffer
lda #$00
sta C3PO
// Restore proper IECPROTO value
; Restore proper IECPROTO value
lda #IEC_JIFFY
sta IECPROTO
#if CONFIG_IEC_JIFFYDOS_BLANK
!ifdef CONFIG_IEC_JIFFYDOS_BLANK {
// Restore screen state
; Restore screen state
lda TBTCNT
sta VIC_SCROLY
#else
} else {
// Re-enable sprites
; Re-enable sprites
lda TBTCNT
sta VIC_SPENA
}
#endif
// Store last byte as unoptimized LOAD routine would
; Store last byte as unoptimized LOAD routine would
stx TBTCNT
// No need to re-enable interrupts; other IEC routines
// called by LOAD will do this nevertheless
; No need to re-enable interrupts; other IEC routines
; called by LOAD will do this nevertheless
// End of load loop
; End of load loop
jmp load_iec_loop_end
#endif // CONFIG_IEC_JIFFYDOS and not CONFIG_MEMORY_MODEL_60K
} } ; CONFIG_IEC_JIFFYDOS and not CONFIG_MEMORY_MODEL_60K
src/kernal/iec_fast/jiffydos_prepare.s
+13 -15
View File
@@ -1,32 +1,30 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// JiffyDOS transfer preparation routine
//
;
; JiffyDOS transfer preparation routine
;
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
jiffydos_prepare:
// We need to preserve 3 lowest bits of CIA2_PRA, they contain important
// data - fortunately, the bits are never changed by external devices
// Use C3PO for this, as afterwards we have to set there 0 nevertheless
; We need to preserve 3 lowest bits of CIA2_PRA, they contain important
; data - fortunately, the bits are never changed by external devices
; Use C3PO for this, as afterwards we have to set there 0 nevertheless
lda CIA2_PRA
and #%00000111
sta C3PO
// Hide sprites; JiffyDOS timing regime is very strict, before transmitting
// anything we need to make sure nothing will steal the cycles
; Hide sprites; JiffyDOS timing regime is very strict, before transmitting
; anything we need to make sure nothing will steal the cycles
lda VIC_SPENA
ldx #$00
stx VIC_SPENA
rts
#endif // CONFIG_IEC_JIFFYDOS
}
src/kernal/iec_fast/jiffydos_rx_byte.s
+51 -53
View File
@@ -1,121 +1,119 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// JiffyDOS protocol support for IEC - byte reception
//
;
; JiffyDOS protocol support for IEC - byte reception
;
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
jiffydos_rx_byte:
// Timing is critical, do not allow interrupts
; Timing is critical, do not allow interrupts
sei
// Store .X and .Y on the stack - preserve them
phx_trash_a
phy_trash_a
; Store .X and .Y on the stack - preserve them
+phx_trash_a
+phy_trash_a
// Store previous sprite status on stack
; Store previous sprite status on stack
jsr jiffydos_prepare
pha
// Wait until device is ready to send (releases CLK)
; Wait until device is ready to send (releases CLK)
jsr iec_wait_for_clk_release
// Prepare 'start sending' message
; Prepare 'start sending' message
lda CIA2_PRA
and #$FF - BIT_CIA2_PRA_DAT_OUT // release
and #$FF - BIT_CIA2_PRA_DAT_OUT ; release
tax
// Wait for appropriate moment
; Wait for appropriate moment
jsr jiffydos_wait_line
// Ask device to start sending bits
stx CIA2_PRA // cycles: 4
; Ask device to start sending bits
stx CIA2_PRA ; cycles: 4
// Prepare 'data pull' byte, cycles: 3 + 2 + 2 = 7
; Prepare 'data pull' byte, cycles: 3 + 2 + 2 = 7
lda C3PO
ora #BIT_CIA2_PRA_DAT_OUT // pull
ora #BIT_CIA2_PRA_DAT_OUT ; pull
tax
// Delay, JiffyDOS needs some time, 4 cycles
nop
nop
; Delay, JiffyDOS needs some time, 4 cycles
+nop
+nop
// Get bits, cycles: 4 + 2 + 2 = 8
lda CIA2_PRA // bits 0 and 1 on CLK/DATA
; Get bits, cycles: 4 + 2 + 2 = 8
lda CIA2_PRA ; bits 0 and 1 on CLK/DATA
lsr
lsr
// Wait for the drive, cycles: 2
nop
; Wait for the drive, cycles: 2
+nop
// Get bits, cycles: 4 + 2 + 2 = 8
ora CIA2_PRA // bits 2 and 3 on CLK/DATA
; Get bits, cycles: 4 + 2 + 2 = 8
ora CIA2_PRA ; bits 2 and 3 on CLK/DATA
lsr
lsr
// Get bits, cycles: 3 + 4 + 2 + 2 = 11
; Get bits, cycles: 3 + 4 + 2 + 2 = 11
eor C3PO
eor CIA2_PRA // bits 4 and 5 on CLK/DATA
eor CIA2_PRA ; bits 4 and 5 on CLK/DATA
lsr
lsr
// Get bits, cycles: 3 + 4 = 7
; Get bits, cycles: 3 + 4 = 7
eor C3PO
eor CIA2_PRA // bits 6 and 7 on CLK/DATA
eor CIA2_PRA ; bits 6 and 7 on CLK/DATA
// Preserve read byte, cycles: 3
sta TBTCNT // $A4 is a byte buffer according to http://sta.c64.org/cbm64mem.html
; Preserve read byte, cycles: 3
sta TBTCNT ; $A4 is a byte buffer according to http://sta.c64.org/cbm64mem.html
// Delay, JiffyDOS needs some time; for PAL one NOP would be enough,
// but NTSC machines are clocked slightly faster; cycles: 4
nop
nop
; Delay, JiffyDOS needs some time; for PAL one NOP would be enough,
; but NTSC machines are clocked slightly faster; cycles: 4
+nop
+nop
// Retrieve status bits, cycles: 4
; Retrieve status bits, cycles: 4
bit CIA2_PRA
// Pull DATA at the end, cycles: 4
; Pull DATA at the end, cycles: 4
stx CIA2_PRA
// If CLK line active - success
; If CLK line active - success
bvc jiffydos_rx_byte_end
// EOI or error, released DATA (highest byte set to 1) means error - see protocol analysis by Michael Steil, step R7a
; EOI or error, released DATA (highest byte set to 1) means error - see protocol analysis by Michael Steil, step R7a
lda CIA2_PRA
bmi jiffydos_rx_byte_error
// EOI - no error
; EOI - no error
jsr kernalstatus_EOI
// FALLTROUGH
; FALLTROUGH
jiffydos_rx_byte_end:
// Indicate that no byte waits in output buffer
; Indicate that no byte waits in output buffer
lda #$00
sta C3PO
// Restore proper IECPROTO value
; Restore proper IECPROTO value
lda #IEC_JIFFY
sta IECPROTO
// Re-enable sprites
; Re-enable sprites
pla
sta VIC_SPENA
// End byte reception
; End byte reception
jmp iec_rx_end
jiffydos_rx_byte_error:
jsr kernalerror_IEC_TIMEOUT_READ
bcs jiffydos_rx_byte_end // branch always
#endif // CONFIG_IEC_JIFFYDOS
bcs jiffydos_rx_byte_end ; branch always
}
src/kernal/iec_fast/jiffydos_tx_byte.s
+45 -47
View File
@@ -1,97 +1,97 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// JiffyDOS protocol support for IEC - byte transfer
//
;
; JiffyDOS protocol support for IEC - byte transfer
;
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
jiffydos_tx_byte:
// Timing is critical, do not allow interrupts
; Timing is critical, do not allow interrupts
sei
// If EOI requested (carry flag set), mark this in IECPROTO as 0
bcc !+
dec IECPROTO // turns 1 into 0
!:
// Store .X and .Y on the stack - preserve them
phx_trash_a
phy_trash_a
; If EOI requested (carry flag set), mark this in IECPROTO as 0
bcc @1
dec IECPROTO ; turns 1 into 0
@1:
; Store .X and .Y on the stack - preserve them
+phx_trash_a
+phy_trash_a
// Make sure we are not sending data on ATN
; Make sure we are not sending data on ATN
jsr iec_release_atn
// Store previous sprite status on stack
; Store previous sprite status on stack
jsr jiffydos_prepare
pha
// Prepare nibbles to send
; Prepare nibbles to send
lda TBTCNT
and #$0F
tax
lda jiffydos_bittable, X // low nibble has to be encoded
lda jiffydos_bittable, X ; low nibble has to be encoded
pha
lda TBTCNT
and #$F0
pha
// Prepare value for device notification
; Prepare value for device notification
ldx C3PO
// Wait till receiver is ready
; Wait till receiver is ready
jsr iec_wait_for_data_release
// Wait till it is safe to send data
; Wait till it is safe to send data
jsr jiffydos_wait_line
// Notify device that we are going to send byte by releasing everything
stx CIA2_PRA // cycles: 4
// Send high nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 3 + 4 = 24
pla // retrieve high nibble from stack
ora C3PO // restore VIC-II and RS-232 bits
sta CIA2_PRA // bits 4 and 5 on CLK/DATA
lsr // move bits 6 and 7 to positions 4 and 5
; Notify device that we are going to send byte by releasing everything
stx CIA2_PRA ; cycles: 4
; Send high nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 3 + 4 = 24
pla ; retrieve high nibble from stack
ora C3PO ; restore VIC-II and RS-232 bits
sta CIA2_PRA ; bits 4 and 5 on CLK/DATA
lsr ; move bits 6 and 7 to positions 4 and 5
lsr
and #%00110000 // clear everything but CLK/DATA
and #%00110000 ; clear everything but CLK/DATA
ora C3PO
sta CIA2_PRA // bits 6 and 7 on CLK/DATA
sta CIA2_PRA ; bits 6 and 7 on CLK/DATA
// Send low nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 4 = 21
pla // retrieve low nibble from stack
ora C3PO // restore VIC-II and RS-232 bits
; Send low nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 4 = 21
pla ; retrieve low nibble from stack
ora C3PO ; restore VIC-II and RS-232 bits
sta CIA2_PRA
lsr
lsr
and #%00110000 // clear everything but CLK/DATA
and #%00110000 ; clear everything but CLK/DATA
sta CIA2_PRA
// Signal EOI if needed; cycles till no EOI: 3 + 3 + 2 + 2 + 4 = 14
; Signal EOI if needed; cycles till no EOI: 3 + 3 + 2 + 2 + 4 = 14
lda C3PO
ldx IECPROTO
beq jiffydos_tx_byte_wait_eoi
// FALLTROUGH
; FALLTROUGH
jiffydos_tx_byte_finalize:
ora #BIT_CIA2_PRA_CLK_OUT // pull CLK
ora #BIT_CIA2_PRA_CLK_OUT ; pull CLK
sta CIA2_PRA
// Restore proper IECPROTO value
; Restore proper IECPROTO value
lda #IEC_JIFFY
sta IECPROTO
// Re-enable sprites and interrupts
; Re-enable sprites and interrupts
pla
sta VIC_SPENA
cli
// Return success
; Return success
jmp iec_return_success
@@ -101,11 +101,9 @@ jiffydos_tx_byte_wait_eoi:
jsr iec_wait20us
lda C3PO
// According to protocol analysis by Michael Steil (step S8) we should pull the DATA here
// to signal there was no error; but DATA pulled by the controller is a normal state
// (which should be stored in C3PO), so there is nothing to do here.
; According to protocol analysis by Michael Steil (step S8) we should pull the DATA here
; to signal there was no error; but DATA pulled by the controller is a normal state
; (which should be stored in C3PO), so there is nothing to do here.
jmp jiffydos_tx_byte_finalize
#endif // CONFIG_IEC_JIFFYDOS
}
src/kernal/iec_fast/jiffydos_wait_line.s
+19 -21
View File
@@ -1,37 +1,35 @@
// #LAYOUT# STD * #TAKE
// #LAYOUT# * KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# STD * #TAKE
;; #LAYOUT# * KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// JiffyDOS helper routine to wait for appropriate moment,
// where no badline will interrupt the transmission
//
;
; JiffyDOS helper routine to wait for appropriate moment,
; where no badline will interrupt the transmission
;
#if CONFIG_IEC_JIFFYDOS
!ifdef CONFIG_IEC_JIFFYDOS {
jiffydos_wait_line:
// One might try to optimize the code by checking for disabled screen
// (bit 4 of VIC_SCROLY); problem: VIC checks this bit only once per frame:
// - https://www.lemon64.com/forum/viewtopic.php?t=56582
// so it would complicated the code
; One might try to optimize the code by checking for disabled screen
; (bit 4 of VIC_SCROLY); problem: VIC checks this bit only once per frame:
; - https://www.lemon64.com/forum/viewtopic.php?t=56582
; so it would complicated the code
// Avoid 2 lines before the badline, otherwise VIC will ruin the synchronization
; Avoid 2 lines before the badline, otherwise VIC will ruin the synchronization
lda VIC_RASTER
cmp #$2E
bcc jiffydos_wait_line_done // we are safe, border - lot of time till badline
!:
lda VIC_RASTER // carry+ is definitely set here!
bcc jiffydos_wait_line_done ; we are safe, border - lot of time till badline
@1:
lda VIC_RASTER ; carry+ is definitely set here!
sbc VIC_SCROLY
and #$07 // we want 8 lowest bits
and #$07 ; we want 8 lowest bits
cmp #$06
bcs !-
bcs @1
jiffydos_wait_line_done:
rts
#endif // CONFIG_IEC_JIFFYDOS
}
src/kernal/iec_fast/m65dos_bridge.s
+57 -49
View File
@@ -1,98 +1,106 @@
// #LAYOUT# M65 KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# M65 KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// MEGA65 pseudo-IEC internal DOS support
//
;
; MEGA65 pseudo-IEC internal DOS support
;
.label VDOS_INIT = $4000 + 0 * 2
.label VDOS_CHKUNIT = $4000 + 1 * 2
.label VDOS_SETUNIT = $4000 + 2 * 2
.label VDOS_ACPTR = $4000 + 3 * 2
.label VDOS_CIOUT = $4000 + 4 * 2
.label VDOS_LISTEN = $4000 + 5 * 2
.label VDOS_SECOND = $4000 + 6 * 2
.label VDOS_TALK = $4000 + 7 * 2
.label VDOS_TKSA = $4000 + 8 * 2
.label VDOS_UNTLK = $4000 + 9 * 2
.label VDOS_UNLSN = $4000 + 10 * 2
!addr VDOS_INIT = $4000 + 0 * 2
!addr VDOS_CHKUNIT = $4000 + 1 * 2
!addr VDOS_SETUNIT = $4000 + 2 * 2
!addr VDOS_ACPTR = $4000 + 3 * 2
!addr VDOS_CIOUT = $4000 + 4 * 2
!addr VDOS_LISTEN = $4000 + 5 * 2
!addr VDOS_SECOND = $4000 + 6 * 2
!addr VDOS_TALK = $4000 + 7 * 2
!addr VDOS_TKSA = $4000 + 8 * 2
!addr VDOS_UNTLK = $4000 + 9 * 2
!addr VDOS_UNLSN = $4000 + 10 * 2
m65dos_init:
// Initializes the DOS internal variables
; Initializes the DOS internal variables
jsr map_DOS_1
jsr_ind VDOS_INIT
jmp_8 !+
jsr (VDOS_INIT)
bra m65dos_end_1
m65dos_chkunit: // XXX expose to BASIC
m65dos_chkunit: ; XXX expose to BASIC
// Checks is the unit number is supported by the internal DOS
// Input: .A - unit number to check
// Output: Carry set if not supported, otherwise .A contains unit type (0 = SD card, 1 = internal floppy, 2 = RAM disk)
; Checks is the unit number is supported by the internal DOS
; Input: .A - unit number to check
; Output: Carry set if not supported, otherwise .A contains unit type (0 = SD card, 1 = internal floppy, 2 = RAM disk)
jsr map_DOS_1
jsr_ind VDOS_CHKUNIT
jmp_8 !+
jsr (VDOS_CHKUNIT)
bra m65dos_end_1
m65dos_setunit: // XXX expose to BASIC
m65dos_setunit: ; XXX expose to BASIC
// Set the unit number
// Input: .A - unit number, .X - unit type (as in m65dos_chkunit)
// Output: Carry set means error
; Set the unit number
; Input: .A - unit number, .X - unit type (as in m65dos_chkunit)
; Output: Carry set means error
jsr map_DOS_1
jsr_ind VDOS_SETUNIT
jmp_8 !+
jsr (VDOS_SETUNIT)
bra m65dos_end_1
m65dos_acptr:
jsr map_DOS_1
jsr_ind VDOS_ACPTR
!:
jmp map_NORMAL_from_DOS_1 // ACPTR is slightly faster
jsr (VDOS_ACPTR)
; FALLTROUGH
m65dos_end_1:
jmp map_NORMAL_from_DOS_1 ; ACPTR is slightly faster
m65dos_ciout:
jsr map_DOS_1
jsr_ind VDOS_CIOUT
!:
jmp map_NORMAL_from_DOS_1 // CIOUT is slightly faster
jsr (VDOS_CIOUT)
; FALLTROUGH
m65dos_end_2:
jmp map_NORMAL_from_DOS_1 ; CIOUT is slightly faster
m65dos_listen:
jsr map_DOS_1
jsr_ind VDOS_LISTEN
jmp_8 !-
jsr (VDOS_LISTEN)
bra m65dos_end_2
m65dos_second:
jsr map_DOS_1
jsr_ind VDOS_SECOND
jmp_8 !-
jsr (VDOS_SECOND)
bra m65dos_end_2
m65dos_talk:
jsr map_DOS_1
jsr_ind VDOS_TALK
jmp_8 !-
jsr (VDOS_TALK)
bra m65dos_end_2
m65dos_tksa:
jsr map_DOS_1
jsr_ind VDOS_TKSA
jmp_8 !-
jsr (VDOS_TKSA)
bra m65dos_end_2
m65dos_untlk:
jsr map_DOS_1
jsr_ind VDOS_UNTLK
jmp_8 !-
jsr (VDOS_UNTLK)
bra m65dos_end_2
m65dos_unlsn:
jsr map_DOS_1
jsr_ind VDOS_UNLSN
jmp_8 !-
jsr (VDOS_UNLSN)
bra m65dos_end_2
src/kernal/iec_fast/m65dos_check.s
+7 -7
View File
@@ -1,9 +1,9 @@
// #LAYOUT# M65 KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# M65 KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// MEGA65 pseudo-IEC internal DOS support - check if the current device is already handled by internal DOS
//
;
; MEGA65 pseudo-IEC internal DOS support - check if the current device is already handled by internal DOS
;
m65dos_check:
@@ -11,12 +11,12 @@ m65dos_check:
pha
lda IECPROTO
cmp #IEC_ROMDOS
beq !+
beq @1
pla
sec
rts
!:
@1:
pla
clc
rts
src/kernal/iec_fast/m65dos_detect.s
+9 -9
View File
@@ -1,22 +1,22 @@
// #LAYOUT# M65 KERNAL_0 #TAKE
// #LAYOUT# * * #IGNORE
;; #LAYOUT# M65 KERNAL_0 #TAKE
;; #LAYOUT# * * #IGNORE
//
// MEGA65 pseudo-IEC internal DOS support - detect if a drive should be handled by internal DOS
//
;
; MEGA65 pseudo-IEC internal DOS support - detect if a drive should be handled by internal DOS
;
m65dos_detect:
// Checks if drive is supported by internal DOS
// Output: Carry set if not supported, if supported IECPROTO isset to IEC_ROMDOS
; Checks if drive is supported by internal DOS
; Output: Carry set if not supported, if supported IECPROTO isset to IEC_ROMDOS
pha
jsr m65dos_chkunit
bcs !+
bcs @1
lda #IEC_ROMDOS
sta IECPROTO
!:
@1:
pla
rts