From d5f3d1386621797cb9e800a7997782447f6d1ee2 Mon Sep 17 00:00:00 2001
From: FeralChild64 <you@example.com>
Date: Mon, 4 Jan 2021 18:49:51 +0100
Subject: [PATCH] implemented several Z80 addressing modes

---
 src/zvm_m65/,aliases_zvm.s         | 61 +++++++++++++++++++++++++++---
 src/zvm_m65/z80_instr_exchange.s   | 12 +++---
 src/zvm_m65/z80_instr_load_16bit.s | 10 ++---
 src/zvm_m65/z80_instr_load_8bit.s  |  6 +--
 4 files changed, 69 insertions(+), 20 deletions(-)

diff --git a/src/zvm_m65/,aliases_zvm.s b/src/zvm_m65/,aliases_zvm.s
index 4cd0547b..2cf8a4d1 100644
--- a/src/zvm_m65/,aliases_zvm.s
+++ b/src/zvm_m65/,aliases_zvm.s
@@ -173,15 +173,64 @@
 	sta [REG_HL], z
 }
 
+!macro Z80_FETCH_VIA_nn {                        ; fetch to .A from ((PC))
+
+	lda [REG_PC], z
+	sta PTR_DATA+0
+	inw REG_PC
+	lda [REG_PC], z
+	sta PTR_DATA+1
+	inw REG_PC
+
+	lda [PTR_DATA], z
+}
+
+!macro Z80_STORE_VIA_nn {                        ; store .X to ((PC))
+
+	lda [REG_PC], z
+	sta PTR_DATA+0
+	inw REG_PC
+	lda [REG_PC], z
+	sta PTR_DATA+1
+	inw REG_PC
+
+	txa
+	lda [PTR_DATA], z
+}
+
+!macro Z80_FETCH_VIA_plus1 {                     ; fetch to .A from [PTR_DATA+1]
+
+	inw PTR_DATA
+	lda [PTR_DATA], z
+}
+
+!macro Z80_STORE_VIA_plus1 {                     ; store .A to [PTR_DATA+1]
+
+	inw PTR_DATA
+	sta [PTR_DATA], z
+}
+
+!macro Z80_XCHG_VIA_SP_lo {                      ; for exchange via stack only
+
+	lda [REG_SP], z
+	tay
+	txa
+	sta [REG_SP], z 
+}
+
+!macro Z80_XCHG_VIA_SP_hi {                      ; for exchange via stack only
+
+	inz
+	lda [REG_SP], z
+	tay
+	txa
+	sta [REG_SP], z
+	dez
+}
+
 ; XXX turn vectors below into macros
 
 !addr VEC_fetch_via_IX_d     = $52
 !addr VEC_fetch_via_IY_d     = $54
 !addr VEC_store_via_IX_d     = $56
 !addr VEC_store_via_IY_d     = $58
-!addr VEC_fetch_via_nn       = $5A
-!addr VEC_store_via_nn       = $5C
-!addr VEC_fetch_via_plus1    = $5E
-!addr VEC_store_via_plus1    = $60  ; XXX jump to next directly?
-!addr VEC_xchng_stack_lo     = $62
-!addr VEC_xchng_stack_hi     = $64
diff --git a/src/zvm_m65/z80_instr_exchange.s b/src/zvm_m65/z80_instr_exchange.s
index 0893f413..0471c1f5 100644
--- a/src/zvm_m65/z80_instr_exchange.s
+++ b/src/zvm_m65/z80_instr_exchange.s
@@ -67,12 +67,12 @@ Z80_instr_D9:      ; EXX
 	jmp ZVM_next
 
 !macro Z80_EX_VIA_SP_REGnn .REGnn {
-	lda .REGnn+0
-	jsr (VEC_xchng_stack_lo)
-	sta .REGnn+0
-	lda .REGnn+1
-	jsr (VEC_xchng_stack_hi)
-	sta .REGnn+1
+	ldx .REGnn+0
+	+Z80_XCHG_VIA_SP_lo
+	sty .REGnn+0
+	ldx .REGnn+1
+	+Z80_XCHG_VIA_SP_hi
+	sty .REGnn+1
 
 	jmp ZVM_next
 }
diff --git a/src/zvm_m65/z80_instr_load_16bit.s b/src/zvm_m65/z80_instr_load_16bit.s
index e7fb9dbb..c7a6c335 100644
--- a/src/zvm_m65/z80_instr_load_16bit.s
+++ b/src/zvm_m65/z80_instr_load_16bit.s
@@ -32,10 +32,10 @@ Z80_instr_DD_F9:   +Z80_LD_REGnn_REGnn REG_SP, REG_IX                          ;
 Z80_instr_FD_F9:   +Z80_LD_REGnn_REGnn REG_SP, REG_IY                          ; LD SP,IY
 
 !macro Z80_LD_VIA_nn_REGnn .REGnn {
-	lda .REGnn+0
-	jsr (VEC_store_via_nn)
+	ldx .REGnn+0
+	+Z80_STORE_VIA_nn
 	lda .REGnn+1
-	jsr (VEC_store_via_plus1)
+	+Z80_STORE_VIA_plus1
 	jmp ZVM_next	
 }
 
@@ -48,9 +48,9 @@ Z80_instr_FD_22:   +Z80_LD_VIA_nn_REGnn REG_IY                                 ;
 Z80_instr_ED_73:   +Z80_LD_VIA_nn_REGnn REG_SP                                 ; LD (nn),SP
 
 !macro Z80_LD_REGnn_VIA_nn .REGnn {
-	jsr (VEC_fetch_via_nn)
+	+Z80_FETCH_VIA_nn
 	sta .REGnn+0
-	jsr (VEC_fetch_via_plus1)
+	+Z80_FETCH_VIA_plus1
 	sta .REGnn+1
 	jmp ZVM_next	
 }
diff --git a/src/zvm_m65/z80_instr_load_8bit.s b/src/zvm_m65/z80_instr_load_8bit.s
index 08c42fbc..4cb82ffc 100644
--- a/src/zvm_m65/z80_instr_load_8bit.s
+++ b/src/zvm_m65/z80_instr_load_8bit.s
@@ -182,13 +182,13 @@ Z80_instr_1A:                                                                  ;
 
 Z80_instr_32:                                                                  ; LD (nn),A
 
-	lda REG_A
-	jsr (VEC_store_via_nn)
+	ldx REG_A
+	+Z80_STORE_VIA_nn
 	jmp ZVM_next
 
 Z80_instr_3A:                                                                  ; LD A,(nn)
 
-	jsr (VEC_fetch_via_nn)
+	+Z80_FETCH_VIA_nn
 	sta REG_A
 	jmp ZVM_next