more work on Z80 opcodes
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FeralChild64 committed
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@@ -27,11 +27,8 @@ ZVM_store_next:
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}
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; unimplemented/illegal instructions
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Z80_illegal__DD:
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Z80_illegal__ED:
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Z80_illegal__FD:
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Z80_illegal__xDCB:
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; unsupported illegal instructions
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Z80_unsupported:
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; XXX add a separate handler for illegal instructions
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; LD instructions with no effect
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Z80_instr_40: ; LD B,B
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@@ -41,7 +38,11 @@ Z80_instr_5B: ;
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Z80_instr_64: ; LD H,H
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Z80_instr_6D: ; LD L,L
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Z80_instr_7F: ; LD A,A
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; For interrupts (not emulated as of yet)
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Z80_illeg_DD_64: ; LD IXH,IXH
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Z80_illeg_DD_6D: ; LD IXL,IXL
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Z80_illeg_FD_64: ; LD IYH,IYH
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Z80_illeg_FD_6D: ; LD IYL,IYL
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; For interrupts (emulation not needed for CP/M)
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Z80_instr_ED_46: ; IM 0
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Z80_illeg_ED_4E: ; IM 0
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Z80_illeg_ED_66: ; IM 0
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@@ -90,7 +91,6 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ;
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;
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@@ -100,18 +100,12 @@ Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ;
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Z80_instr_DD_CB: ; #DDCB
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Z80_instr_FD_CB: ; #FDCB
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Z80_instr_02: ; LD (BC),A
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Z80_instr_09: ; ADD HL,BC
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Z80_instr_0A: ; LD A,(BC)
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Z80_instr_12: ; LD (DE),A
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Z80_instr_19: ; ADD HL,DE
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Z80_instr_1A: ; LD A,(DE)
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Z80_instr_22: ; LD (nn),HL
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Z80_instr_29: ; ADD HL,HL
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Z80_instr_2A: ; LD HL,(nn)
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Z80_instr_32: ; LD (nn),A
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Z80_instr_39: ; ADD HL,SP
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Z80_instr_3A: ; LD A,(nn)
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Z80_instr_80: ; ADD A,B
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Z80_instr_81: ; ADD A,C
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Z80_instr_82: ; ADD A,D
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@@ -152,39 +146,13 @@ Z80_instr_BC: ; CP H
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Z80_instr_BD: ; CP L
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Z80_instr_BE: ; CP (HL)
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Z80_instr_BF: ; CP A
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Z80_instr_C0: ; RET NZ
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Z80_instr_C4: ; CALL NZ,nn
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Z80_instr_C6: ; ADD A,n
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Z80_instr_C7: ; RST 00H
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Z80_instr_C8: ; RET z
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Z80_instr_C9: ; RET
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Z80_instr_CC: ; CALL Z,nn
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Z80_instr_CD: ; CALL nn
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Z80_instr_CE: ; ADC A,n
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Z80_instr_CF: ; RST 08H
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Z80_instr_D0: ; RET NC
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Z80_instr_D4: ; CALL NC,nn
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Z80_instr_D6: ; SUB n
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Z80_instr_D7: ; RST 10H
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Z80_instr_D8: ; RET C
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Z80_instr_DC: ; CALL C,nn
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Z80_instr_DE: ; SBC A,n
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Z80_instr_DF: ; RST 18H
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Z80_instr_E0: ; RET PO
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Z80_instr_E3: ; EX (SP),HL
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Z80_instr_E4: ; CALL PO,nn
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Z80_instr_E7: ; RST 20H
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Z80_instr_E8: ; RET PE
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Z80_instr_EC: ; CALL PE,nn
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Z80_instr_EF: ; RST 28H
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Z80_instr_F0: ; RET P
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Z80_instr_F4: ; CALL P,nn
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Z80_instr_F7: ; RST 30H
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Z80_instr_F8: ; RET M
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Z80_instr_F9: ; LD SP,HL
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Z80_instr_FC: ; CALL M,nn
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Z80_instr_FE: ; CP n
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Z80_instr_FF: ; RST 38H
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Z80_instr_CB_00: ; RLC B
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Z80_instr_CB_01: ; RLC C
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Z80_instr_CB_02: ; RLC D
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@@ -247,20 +215,6 @@ Z80_instr_DD_22: ; LD (nn),IX
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Z80_instr_DD_29: ; ADD IX,IX
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Z80_instr_DD_2A: ; LD IX,(nn)
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Z80_instr_DD_39: ; ADD IX,SP
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Z80_instr_DD_46: ; LD B,(IX+d)
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Z80_instr_DD_4E: ; LD C,(IX+d)
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Z80_instr_DD_56: ; LD D,(IX+d)
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Z80_instr_DD_5E: ; LD E,(IX+d)
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Z80_instr_DD_66: ; LD H,(IX+d)
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Z80_instr_DD_6E: ; LD L,(IX+d)
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Z80_instr_DD_70: ; LD (IX+d),B
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Z80_instr_DD_71: ; LD (IX+d),C
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Z80_instr_DD_72: ; LD (IX+d),D
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Z80_instr_DD_73: ; LD (IX+d),E
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Z80_instr_DD_74: ; LD (IX+d),H
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Z80_instr_DD_75: ; LD (IX+d),L
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Z80_instr_DD_77: ; LD (IX+d),A
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Z80_instr_DD_7E: ; LD A,(IX+d)
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Z80_instr_DD_86: ; ADD A,(IX+d)
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Z80_instr_DD_8E: ; ADC A,(IX+d)
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Z80_instr_DD_96: ; SUB (IX+d)
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@@ -270,10 +224,8 @@ Z80_instr_DD_E3: ; EX (SP),IX
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Z80_instr_DD_F9: ; LD SP,IX
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Z80_instr_ED_42: ; SBC HL,BC
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Z80_instr_ED_43: ; LD (nn),BC
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Z80_instr_ED_45: ; RETN
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Z80_instr_ED_4A: ; ADC HL,BC
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Z80_instr_ED_4B: ; LD BC,(nn)
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Z80_instr_ED_4D: ; RETTI
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Z80_instr_ED_52: ; SBC HL,DE
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Z80_instr_ED_53: ; LD (nn),DE
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Z80_instr_ED_5A: ; ADC HL,DE
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@@ -308,20 +260,6 @@ Z80_instr_FD_22: ; LD (nn),IY
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Z80_instr_FD_29: ; ADD IY,IY
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Z80_instr_FD_2A: ; LD IY,(nn)
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Z80_instr_FD_39: ; ADD IY,SP
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Z80_instr_FD_46: ; LD B,(IY+d)
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Z80_instr_FD_4E: ; LD C,(IY+d)
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Z80_instr_FD_56: ; LD D,(IY+d)
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Z80_instr_FD_5E: ; LD E,(IY+d)
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Z80_instr_FD_66: ; LD H,(IY+d)
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Z80_instr_FD_6E: ; LD L,(IY+d)
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Z80_instr_FD_70: ; LD (IY+d),B
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Z80_instr_FD_71: ; LD (IY+d),C
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Z80_instr_FD_72: ; LD (IY+d),D
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Z80_instr_FD_73: ; LD (IY+d),E
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Z80_instr_FD_74: ; LD (IY+d),H
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Z80_instr_FD_75: ; LD (IY+d),L
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Z80_instr_FD_77: ; LD (IY+d),A
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Z80_instr_FD_7E: ; LD A,(IY+d)
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Z80_instr_FD_86: ; ADD A,(IY+d)
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Z80_instr_FD_8E: ; ADC A,(IY+d)
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Z80_instr_FD_96: ; SUB (IY+d)
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@@ -344,14 +282,143 @@ Z80_illeg_CB_34: ; SLL H
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Z80_illeg_CB_35: ; SLL L
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Z80_illeg_CB_36: ; SLL (HL)
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Z80_illeg_CB_37: ; SLL A
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Z80_illeg_ED_55: ; RETN
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Z80_illeg_ED_5D: ; RETN
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Z80_illeg_ED_65: ; RETN
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Z80_illeg_ED_6D: ; RETN
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Z80_illeg_ED_70: ; IN F,(C)
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Z80_illeg_ED_71: ; OUT (C),0
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Z80_illeg_ED_75: ; RETN
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Z80_illeg_ED_7D: ; RETN
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Z80_illeg_ED_63: ; LD (nn),HL
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Z80_illeg_ED_6B: ; LD HL,(nn)
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Z80_illeg_DD_84: ; ADD A,IXH
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Z80_illeg_DD_85: ; ADD A,IXL
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Z80_illeg_DD_8C: ; ADC A,IXH
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Z80_illeg_DD_8D: ; ADC A,IXL
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Z80_illeg_DD_94: ; SUB A,IXH
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Z80_illeg_DD_95: ; SUB A,IXL
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Z80_illeg_DD_9C: ; SBC A,IXH
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Z80_illeg_DD_9D: ; SBC A,IXL
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Z80_illeg_DD_BC: ; CP IXH
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Z80_illeg_DD_BD: ; CP IXL
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Z80_illeg_FD_84: ; ADD A,IYH
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Z80_illeg_FD_85: ; ADD A,IYL
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Z80_illeg_FD_8C: ; ADC A,IYH
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Z80_illeg_FD_8D: ; ADC A,IYL
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Z80_illeg_FD_94: ; SUB A,IYH
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Z80_illeg_FD_95: ; SUB A,IYL
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Z80_illeg_FD_9C: ; SBC A,IYH
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Z80_illeg_FD_9D: ; SBC A,IYL
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Z80_illeg_FD_BC: ; CP IYH
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Z80_illeg_FD_BD: ; CP IYL
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Z80_illeg_xDCB_00: ; RLC (IXY+d),B
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Z80_illeg_xDCB_01: ; RLC (IXY+d),C
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Z80_illeg_xDCB_02: ; RLC (IXY+d),D
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Z80_illeg_xDCB_03: ; RLC (IXY+d),E
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Z80_illeg_xDCB_04: ; RLC (IXY+d),H
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Z80_illeg_xDCB_05: ; RLC (IXY+d),L
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Z80_illeg_xDCB_07: ; RLC (IXY+d),A
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Z80_illeg_xDCB_08: ; RRC (IXY+d),B
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Z80_illeg_xDCB_09: ; RRC (IXY+d),C
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Z80_illeg_xDCB_0A: ; RRC (IXY+d),D
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Z80_illeg_xDCB_0B: ; RRC (IXY+d),E
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Z80_illeg_xDCB_0C: ; RRC (IXY+d),H
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Z80_illeg_xDCB_0D: ; RRC (IXY+d),L
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Z80_illeg_xDCB_0F: ; RRC (IXY+d),A
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Z80_illeg_xDCB_10: ; RL (IXY+d),B
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Z80_illeg_xDCB_11: ; RL (IXY+d),C
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Z80_illeg_xDCB_12: ; RL (IXY+d),D
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Z80_illeg_xDCB_13: ; RL (IXY+d),E
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Z80_illeg_xDCB_14: ; RL (IXY+d),H
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Z80_illeg_xDCB_15: ; RL (IXY+d),L
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Z80_illeg_xDCB_17: ; RL (IXY+d),A
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Z80_illeg_xDCB_18: ; RR (IXY+d),B
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Z80_illeg_xDCB_19: ; RR (IXY+d),C
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Z80_illeg_xDCB_1A: ; RR (IXY+d),D
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Z80_illeg_xDCB_1B: ; RR (IXY+d),E
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Z80_illeg_xDCB_1C: ; RR (IXY+d),H
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Z80_illeg_xDCB_1D: ; RR (IXY+d),L
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Z80_illeg_xDCB_1F: ; RR (IXY+d),A
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Z80_illeg_xDCB_20: ; SLA (IXY+d),B
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Z80_illeg_xDCB_21: ; SLA (IXY+d),C
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Z80_illeg_xDCB_22: ; SLA (IXY+d),D
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Z80_illeg_xDCB_23: ; SLA (IXY+d),E
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Z80_illeg_xDCB_24: ; SLA (IXY+d),H
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Z80_illeg_xDCB_25: ; SLA (IXY+d),L
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Z80_illeg_xDCB_27: ; SLA (IXY+d),A
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Z80_illeg_xDCB_28: ; SRA (IXY+d),B
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Z80_illeg_xDCB_29: ; SRA (IXY+d),C
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Z80_illeg_xDCB_2A: ; SRA (IXY+d),D
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Z80_illeg_xDCB_2B: ; SRA (IXY+d),E
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Z80_illeg_xDCB_2C: ; SRA (IXY+d),H
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Z80_illeg_xDCB_2D: ; SRA (IXY+d),L
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Z80_illeg_xDCB_2F: ; SRA (IXY+d),A
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Z80_illeg_xDCB_30: ; SLL (IXY+d),B
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Z80_illeg_xDCB_31: ; SLL (IXY+d),C
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Z80_illeg_xDCB_32: ; SLL (IXY+d),D
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Z80_illeg_xDCB_33: ; SLL (IXY+d),E
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Z80_illeg_xDCB_34: ; SLL (IXY+d),H
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Z80_illeg_xDCB_35: ; SLL (IXY+d),L
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Z80_illeg_xDCB_36: ; SLL (IXY+d)
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Z80_illeg_xDCB_37: ; SLL (IXY+d),A
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Z80_illeg_xDCB_38: ; SLR (IXY+d),B
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Z80_illeg_xDCB_39: ; SLR (IXY+d),C
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Z80_illeg_xDCB_3A: ; SLR (IXY+d),D
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Z80_illeg_xDCB_3B: ; SLR (IXY+d),E
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Z80_illeg_xDCB_3C: ; SLR (IXY+d),H
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Z80_illeg_xDCB_3D: ; SLR (IXY+d),L
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Z80_illeg_xDCB_3F: ; SLR (IXY+d),A
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Z80_illeg_xDCB_80: ; RES 0,(IXY+d),B
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Z80_illeg_xDCB_81: ; RES 0,(IXY+d),C
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Z80_illeg_xDCB_82: ; RES 0,(IXY+d),D
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Z80_illeg_xDCB_83: ; RES 0,(IXY+d),E
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Z80_illeg_xDCB_84: ; RES 0,(IXY+d),H
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Z80_illeg_xDCB_85: ; RES 0,(IXY+d),L
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Z80_illeg_xDCB_87: ; RES 0,(IXY+d),A
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Z80_illeg_xDCB_88: ; RES 1,(IXY+d),B
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Z80_illeg_xDCB_89: ; RES 1,(IXY+d),C
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Z80_illeg_xDCB_8A: ; RES 1,(IXY+d),D
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Z80_illeg_xDCB_8B: ; RES 1,(IXY+d),E
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Z80_illeg_xDCB_8C: ; RES 1,(IXY+d),H
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Z80_illeg_xDCB_8D: ; RES 1,(IXY+d),L
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Z80_illeg_xDCB_8F: ; RES 1,(IXY+d),A
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Z80_illeg_xDCB_90: ; RES 2,(IXY+d),B
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Z80_illeg_xDCB_91: ; RES 2,(IXY+d),C
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Z80_illeg_xDCB_92: ; RES 2,(IXY+d),D
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Z80_illeg_xDCB_93: ; RES 2,(IXY+d),E
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Z80_illeg_xDCB_94: ; RES 2,(IXY+d),H
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Z80_illeg_xDCB_95: ; RES 2,(IXY+d),L
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Z80_illeg_xDCB_97: ; RES 2,(IXY+d),A
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Z80_illeg_xDCB_98: ; RES 3,(IXY+d),B
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Z80_illeg_xDCB_99: ; RES 3,(IXY+d),C
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Z80_illeg_xDCB_9A: ; RES 3,(IXY+d),D
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Z80_illeg_xDCB_9B: ; RES 3,(IXY+d),E
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Z80_illeg_xDCB_9C: ; RES 3,(IXY+d),H
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Z80_illeg_xDCB_9D: ; RES 3,(IXY+d),L
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Z80_illeg_xDCB_9F: ; RES 3,(IXY+d),A
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Z80_illeg_xDCB_A0: ; RES 4,(IXY+d),B
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Z80_illeg_xDCB_A1: ; RES 4,(IXY+d),C
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Z80_illeg_xDCB_A2: ; RES 4,(IXY+d),D
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Z80_illeg_xDCB_A3: ; RES 4,(IXY+d),E
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Z80_illeg_xDCB_A4: ; RES 4,(IXY+d),H
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Z80_illeg_xDCB_A5: ; RES 4,(IXY+d),L
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Z80_illeg_xDCB_A7: ; RES 4,(IXY+d),A
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Z80_illeg_xDCB_A8: ; RES 5,(IXY+d),B
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Z80_illeg_xDCB_A9: ; RES 5,(IXY+d),C
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Z80_illeg_xDCB_AA: ; RES 5,(IXY+d),D
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Z80_illeg_xDCB_AB: ; RES 5,(IXY+d),E
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Z80_illeg_xDCB_AC: ; RES 5,(IXY+d),H
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Z80_illeg_xDCB_AD: ; RES 5,(IXY+d),L
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Z80_illeg_xDCB_AF: ; RES 5,(IXY+d),A
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Z80_illeg_xDCB_B0: ; RES 6,(IXY+d),B
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Z80_illeg_xDCB_B1: ; RES 6,(IXY+d),C
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Z80_illeg_xDCB_B2: ; RES 6,(IXY+d),D
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Z80_illeg_xDCB_B3: ; RES 6,(IXY+d),E
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Z80_illeg_xDCB_B4: ; RES 6,(IXY+d),H
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Z80_illeg_xDCB_B5: ; RES 6,(IXY+d),L
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Z80_illeg_xDCB_B7: ; RES 6,(IXY+d),A
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Z80_illeg_xDCB_B8: ; RES 7,(IXY+d),B
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Z80_illeg_xDCB_B9: ; RES 7,(IXY+d),C
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Z80_illeg_xDCB_BA: ; RES 7,(IXY+d),D
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Z80_illeg_xDCB_BB: ; RES 7,(IXY+d),E
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Z80_illeg_xDCB_BC: ; RES 7,(IXY+d),H
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Z80_illeg_xDCB_BD: ; RES 7,(IXY+d),L
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Z80_illeg_xDCB_BF: ; RES 7,(IXY+d),A
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Z80_illeg_xDCB_C0: ; SET 0,(IXY+d),B
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Z80_illeg_xDCB_C1: ; SET 0,(IXY+d),C
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Z80_illeg_xDCB_C2: ; SET 0,(IXY+d),D
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@@ -359,316 +426,55 @@ Z80_illeg_xDCB_C3: ; SET 0,(IXY+d),E
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Z80_illeg_xDCB_C4: ; SET 0,(IXY+d),H
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Z80_illeg_xDCB_C5: ; SET 0,(IXY+d),L
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Z80_illeg_xDCB_C7: ; SET 0,(IXY+d),A
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Z80_illeg_xDCB_C8: ; SET 1,(IXY+d),B
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Z80_illeg_xDCB_C9: ; SET 1,(IXY+d),C
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Z80_illeg_xDCB_CA: ; SET 1,(IXY+d),D
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Z80_illeg_xDCB_CB: ; SET 1,(IXY+d),E
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Z80_illeg_xDCB_CC: ; SET 1,(IXY+d),H
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Z80_illeg_xDCB_CD: ; SET 1,(IXY+d),L
|
||||
Z80_illeg_xDCB_CF: ; SET 1,(IXY+d),A
|
||||
Z80_illeg_xDCB_D0: ; SET 2,(IXY+d),B
|
||||
Z80_illeg_xDCB_D1: ; SET 2,(IXY+d),C
|
||||
Z80_illeg_xDCB_D2: ; SET 2,(IXY+d),D
|
||||
Z80_illeg_xDCB_D3: ; SET 2,(IXY+d),E
|
||||
Z80_illeg_xDCB_D4: ; SET 2,(IXY+d),H
|
||||
Z80_illeg_xDCB_D5: ; SET 2,(IXY+d),L
|
||||
Z80_illeg_xDCB_D7: ; SET 2,(IXY+d),A
|
||||
Z80_illeg_xDCB_D8: ; SET 3,(IXY+d),B
|
||||
Z80_illeg_xDCB_D9: ; SET 3,(IXY+d),C
|
||||
Z80_illeg_xDCB_DA: ; SET 3,(IXY+d),D
|
||||
Z80_illeg_xDCB_DB: ; SET 3,(IXY+d),E
|
||||
Z80_illeg_xDCB_DC: ; SET 3,(IXY+d),H
|
||||
Z80_illeg_xDCB_DD: ; SET 3,(IXY+d),L
|
||||
Z80_illeg_xDCB_DF: ; SET 3,(IXY+d),A
|
||||
Z80_illeg_xDCB_E0: ; SET 4,(IXY+d),B
|
||||
Z80_illeg_xDCB_E1: ; SET 4,(IXY+d),C
|
||||
Z80_illeg_xDCB_E2: ; SET 4,(IXY+d),D
|
||||
Z80_illeg_xDCB_E3: ; SET 4,(IXY+d),E
|
||||
Z80_illeg_xDCB_E4: ; SET 4,(IXY+d),H
|
||||
Z80_illeg_xDCB_E5: ; SET 4,(IXY+d),L
|
||||
Z80_illeg_xDCB_E7: ; SET 4,(IXY+d),A
|
||||
Z80_illeg_xDCB_E8: ; SET 5,(IXY+d),B
|
||||
Z80_illeg_xDCB_E9: ; SET 5,(IXY+d),C
|
||||
Z80_illeg_xDCB_EA: ; SET 5,(IXY+d),D
|
||||
Z80_illeg_xDCB_EB: ; SET 5,(IXY+d),E
|
||||
Z80_illeg_xDCB_EC: ; SET 5,(IXY+d),H
|
||||
Z80_illeg_xDCB_ED: ; SET 5,(IXY+d),L
|
||||
Z80_illeg_xDCB_EF: ; SET 5,(IXY+d),A
|
||||
Z80_illeg_xDCB_F0: ; SET 6,(IXY+d),B
|
||||
Z80_illeg_xDCB_F1: ; SET 6,(IXY+d),C
|
||||
Z80_illeg_xDCB_F2: ; SET 6,(IXY+d),D
|
||||
Z80_illeg_xDCB_F3: ; SET 6,(IXY+d),E
|
||||
Z80_illeg_xDCB_F4: ; SET 6,(IXY+d),H
|
||||
Z80_illeg_xDCB_F5: ; SET 6,(IXY+d),L
|
||||
Z80_illeg_xDCB_F7: ; SET 6,(IXY+d),A
|
||||
Z80_illeg_xDCB_F8: ; SET 7,(IXY+d),B
|
||||
Z80_illeg_xDCB_F9: ; SET 7,(IXY+d),C
|
||||
Z80_illeg_xDCB_FA: ; SET 7,(IXY+d),D
|
||||
Z80_illeg_xDCB_FB: ; SET 7,(IXY+d),E
|
||||
Z80_illeg_xDCB_FC: ; SET 7,(IXY+d),H
|
||||
Z80_illeg_xDCB_FD: ; SET 7,(IXY+d),L
|
||||
Z80_illeg_xDCB_FF: ; SET 7,(IXY+d),A
|
||||
|
||||
jmp ZVM_next ; XXX provide implementation
|
||||
|
||||
jmp ZVM_next ; XXX
|
||||
|
||||
; XXX add illegal instructions for combination of prefixes
|
||||
|
||||
; XXX include these in the table, add mnemonics
|
||||
|
||||
Z80_illeg_ED_63:
|
||||
Z80_illeg_ED_6B:
|
||||
Z80_illeg_DD_24:
|
||||
Z80_illeg_DD_25:
|
||||
Z80_illeg_DD_26:
|
||||
Z80_illeg_DD_2C:
|
||||
Z80_illeg_DD_2D:
|
||||
Z80_illeg_DD_2E:
|
||||
Z80_illeg_DD_44:
|
||||
Z80_illeg_DD_45:
|
||||
Z80_illeg_DD_4C:
|
||||
Z80_illeg_DD_4D:
|
||||
Z80_illeg_DD_54:
|
||||
Z80_illeg_DD_55:
|
||||
Z80_illeg_DD_5C:
|
||||
Z80_illeg_DD_5D:
|
||||
Z80_illeg_DD_60:
|
||||
Z80_illeg_DD_61:
|
||||
Z80_illeg_DD_62:
|
||||
Z80_illeg_DD_63:
|
||||
Z80_illeg_DD_64:
|
||||
Z80_illeg_DD_65:
|
||||
Z80_illeg_DD_67:
|
||||
Z80_illeg_DD_68:
|
||||
Z80_illeg_DD_69:
|
||||
Z80_illeg_DD_6A:
|
||||
Z80_illeg_DD_6B:
|
||||
Z80_illeg_DD_6C:
|
||||
Z80_illeg_DD_6D:
|
||||
Z80_illeg_DD_6F:
|
||||
Z80_illeg_DD_7C:
|
||||
Z80_illeg_DD_6D:
|
||||
Z80_illeg_DD_84:
|
||||
Z80_illeg_DD_85:
|
||||
Z80_illeg_DD_8C:
|
||||
Z80_illeg_DD_8D:
|
||||
Z80_illeg_DD_94:
|
||||
Z80_illeg_DD_95:
|
||||
Z80_illeg_DD_9C:
|
||||
Z80_illeg_DD_9D:
|
||||
Z80_illeg_DD_A4:
|
||||
Z80_illeg_DD_A5:
|
||||
Z80_illeg_DD_AC:
|
||||
Z80_illeg_DD_AD:
|
||||
Z80_illeg_DD_B4:
|
||||
Z80_illeg_DD_B5:
|
||||
Z80_illeg_DD_BC:
|
||||
Z80_illeg_DD_BD:
|
||||
Z80_illeg_FD_24:
|
||||
Z80_illeg_FD_25:
|
||||
Z80_illeg_FD_26:
|
||||
Z80_illeg_FD_2C:
|
||||
Z80_illeg_FD_2D:
|
||||
Z80_illeg_FD_2E:
|
||||
Z80_illeg_FD_44:
|
||||
Z80_illeg_FD_45:
|
||||
Z80_illeg_FD_4C:
|
||||
Z80_illeg_FD_4D:
|
||||
Z80_illeg_FD_54:
|
||||
Z80_illeg_FD_55:
|
||||
Z80_illeg_FD_5C:
|
||||
Z80_illeg_FD_5D:
|
||||
Z80_illeg_FD_60:
|
||||
Z80_illeg_FD_61:
|
||||
Z80_illeg_FD_62:
|
||||
Z80_illeg_FD_63:
|
||||
Z80_illeg_FD_64:
|
||||
Z80_illeg_FD_65:
|
||||
Z80_illeg_FD_67:
|
||||
Z80_illeg_FD_68:
|
||||
Z80_illeg_FD_69:
|
||||
Z80_illeg_FD_6A:
|
||||
Z80_illeg_FD_6B:
|
||||
Z80_illeg_FD_6C:
|
||||
Z80_illeg_FD_6D:
|
||||
Z80_illeg_FD_6F:
|
||||
Z80_illeg_FD_7C:
|
||||
Z80_illeg_FD_6D:
|
||||
Z80_illeg_FD_84:
|
||||
Z80_illeg_FD_85:
|
||||
Z80_illeg_FD_8C:
|
||||
Z80_illeg_FD_8D:
|
||||
Z80_illeg_FD_94:
|
||||
Z80_illeg_FD_95:
|
||||
Z80_illeg_FD_9C:
|
||||
Z80_illeg_FD_9D:
|
||||
Z80_illeg_FD_A4:
|
||||
Z80_illeg_FD_A5:
|
||||
Z80_illeg_FD_AC:
|
||||
Z80_illeg_FD_AD:
|
||||
Z80_illeg_FD_B4:
|
||||
Z80_illeg_FD_B5:
|
||||
Z80_illeg_FD_BC:
|
||||
Z80_illeg_FD_BD:
|
||||
Z80_illeg_xDCB_00:
|
||||
Z80_illeg_xDCB_01:
|
||||
Z80_illeg_xDCB_02:
|
||||
Z80_illeg_xDCB_03:
|
||||
Z80_illeg_xDCB_04:
|
||||
Z80_illeg_xDCB_05:
|
||||
Z80_illeg_xDCB_07:
|
||||
Z80_illeg_xDCB_08:
|
||||
Z80_illeg_xDCB_09:
|
||||
Z80_illeg_xDCB_0A:
|
||||
Z80_illeg_xDCB_0B:
|
||||
Z80_illeg_xDCB_0C:
|
||||
Z80_illeg_xDCB_0D:
|
||||
Z80_illeg_xDCB_0F:
|
||||
Z80_illeg_xDCB_10:
|
||||
Z80_illeg_xDCB_11:
|
||||
Z80_illeg_xDCB_12:
|
||||
Z80_illeg_xDCB_13:
|
||||
Z80_illeg_xDCB_14:
|
||||
Z80_illeg_xDCB_15:
|
||||
Z80_illeg_xDCB_17:
|
||||
Z80_illeg_xDCB_18:
|
||||
Z80_illeg_xDCB_19:
|
||||
Z80_illeg_xDCB_1A:
|
||||
Z80_illeg_xDCB_1B:
|
||||
Z80_illeg_xDCB_1C:
|
||||
Z80_illeg_xDCB_1D:
|
||||
Z80_illeg_xDCB_1F:
|
||||
Z80_illeg_xDCB_20:
|
||||
Z80_illeg_xDCB_21:
|
||||
Z80_illeg_xDCB_22:
|
||||
Z80_illeg_xDCB_23:
|
||||
Z80_illeg_xDCB_24:
|
||||
Z80_illeg_xDCB_25:
|
||||
Z80_illeg_xDCB_27:
|
||||
Z80_illeg_xDCB_28:
|
||||
Z80_illeg_xDCB_29:
|
||||
Z80_illeg_xDCB_2A:
|
||||
Z80_illeg_xDCB_2B:
|
||||
Z80_illeg_xDCB_2C:
|
||||
Z80_illeg_xDCB_2D:
|
||||
Z80_illeg_xDCB_2F:
|
||||
Z80_illeg_xDCB_30:
|
||||
Z80_illeg_xDCB_31:
|
||||
Z80_illeg_xDCB_32:
|
||||
Z80_illeg_xDCB_33:
|
||||
Z80_illeg_xDCB_34:
|
||||
Z80_illeg_xDCB_35:
|
||||
Z80_illeg_xDCB_36:
|
||||
Z80_illeg_xDCB_37:
|
||||
Z80_illeg_xDCB_38:
|
||||
Z80_illeg_xDCB_39:
|
||||
Z80_illeg_xDCB_3A:
|
||||
Z80_illeg_xDCB_3B:
|
||||
Z80_illeg_xDCB_3C:
|
||||
Z80_illeg_xDCB_3D:
|
||||
Z80_illeg_xDCB_3F:
|
||||
Z80_illeg_xDCB_40:
|
||||
Z80_illeg_xDCB_41:
|
||||
Z80_illeg_xDCB_42:
|
||||
Z80_illeg_xDCB_43:
|
||||
Z80_illeg_xDCB_44:
|
||||
Z80_illeg_xDCB_45:
|
||||
Z80_illeg_xDCB_47:
|
||||
Z80_illeg_xDCB_48:
|
||||
Z80_illeg_xDCB_49:
|
||||
Z80_illeg_xDCB_4A:
|
||||
Z80_illeg_xDCB_4B:
|
||||
Z80_illeg_xDCB_4C:
|
||||
Z80_illeg_xDCB_4D:
|
||||
Z80_illeg_xDCB_4F:
|
||||
Z80_illeg_xDCB_50:
|
||||
Z80_illeg_xDCB_51:
|
||||
Z80_illeg_xDCB_52:
|
||||
Z80_illeg_xDCB_53:
|
||||
Z80_illeg_xDCB_54:
|
||||
Z80_illeg_xDCB_55:
|
||||
Z80_illeg_xDCB_57:
|
||||
Z80_illeg_xDCB_58:
|
||||
Z80_illeg_xDCB_59:
|
||||
Z80_illeg_xDCB_5A:
|
||||
Z80_illeg_xDCB_5B:
|
||||
Z80_illeg_xDCB_5C:
|
||||
Z80_illeg_xDCB_5D:
|
||||
Z80_illeg_xDCB_5F:
|
||||
Z80_illeg_xDCB_60:
|
||||
Z80_illeg_xDCB_61:
|
||||
Z80_illeg_xDCB_62:
|
||||
Z80_illeg_xDCB_63:
|
||||
Z80_illeg_xDCB_64:
|
||||
Z80_illeg_xDCB_65:
|
||||
Z80_illeg_xDCB_67:
|
||||
Z80_illeg_xDCB_68:
|
||||
Z80_illeg_xDCB_69:
|
||||
Z80_illeg_xDCB_6A:
|
||||
Z80_illeg_xDCB_6B:
|
||||
Z80_illeg_xDCB_6C:
|
||||
Z80_illeg_xDCB_6D:
|
||||
Z80_illeg_xDCB_6F:
|
||||
Z80_illeg_xDCB_70:
|
||||
Z80_illeg_xDCB_71:
|
||||
Z80_illeg_xDCB_72:
|
||||
Z80_illeg_xDCB_73:
|
||||
Z80_illeg_xDCB_74:
|
||||
Z80_illeg_xDCB_75:
|
||||
Z80_illeg_xDCB_77:
|
||||
Z80_illeg_xDCB_80:
|
||||
Z80_illeg_xDCB_81:
|
||||
Z80_illeg_xDCB_82:
|
||||
Z80_illeg_xDCB_83:
|
||||
Z80_illeg_xDCB_84:
|
||||
Z80_illeg_xDCB_85:
|
||||
Z80_illeg_xDCB_87:
|
||||
Z80_illeg_xDCB_88:
|
||||
Z80_illeg_xDCB_89:
|
||||
Z80_illeg_xDCB_8A:
|
||||
Z80_illeg_xDCB_8B:
|
||||
Z80_illeg_xDCB_8C:
|
||||
Z80_illeg_xDCB_8D:
|
||||
Z80_illeg_xDCB_8F:
|
||||
Z80_illeg_xDCB_90:
|
||||
Z80_illeg_xDCB_91:
|
||||
Z80_illeg_xDCB_92:
|
||||
Z80_illeg_xDCB_93:
|
||||
Z80_illeg_xDCB_94:
|
||||
Z80_illeg_xDCB_95:
|
||||
Z80_illeg_xDCB_97:
|
||||
Z80_illeg_xDCB_98:
|
||||
Z80_illeg_xDCB_99:
|
||||
Z80_illeg_xDCB_9A:
|
||||
Z80_illeg_xDCB_9B:
|
||||
Z80_illeg_xDCB_9C:
|
||||
Z80_illeg_xDCB_9D:
|
||||
Z80_illeg_xDCB_9F:
|
||||
Z80_illeg_xDCB_A0:
|
||||
Z80_illeg_xDCB_A1:
|
||||
Z80_illeg_xDCB_A2:
|
||||
Z80_illeg_xDCB_A3:
|
||||
Z80_illeg_xDCB_A4:
|
||||
Z80_illeg_xDCB_A5:
|
||||
Z80_illeg_xDCB_A7:
|
||||
Z80_illeg_xDCB_A8:
|
||||
Z80_illeg_xDCB_A9:
|
||||
Z80_illeg_xDCB_AA:
|
||||
Z80_illeg_xDCB_AB:
|
||||
Z80_illeg_xDCB_AC:
|
||||
Z80_illeg_xDCB_AD:
|
||||
Z80_illeg_xDCB_AF:
|
||||
Z80_illeg_xDCB_B0:
|
||||
Z80_illeg_xDCB_B1:
|
||||
Z80_illeg_xDCB_B2:
|
||||
Z80_illeg_xDCB_B3:
|
||||
Z80_illeg_xDCB_B4:
|
||||
Z80_illeg_xDCB_B5:
|
||||
Z80_illeg_xDCB_B7:
|
||||
Z80_illeg_xDCB_B8:
|
||||
Z80_illeg_xDCB_B9:
|
||||
Z80_illeg_xDCB_BA:
|
||||
Z80_illeg_xDCB_BB:
|
||||
Z80_illeg_xDCB_BC:
|
||||
Z80_illeg_xDCB_BD:
|
||||
Z80_illeg_xDCB_BF:
|
||||
Z80_illeg_xDCB_C8:
|
||||
Z80_illeg_xDCB_C9:
|
||||
Z80_illeg_xDCB_CA:
|
||||
Z80_illeg_xDCB_CB:
|
||||
Z80_illeg_xDCB_CC:
|
||||
Z80_illeg_xDCB_CD:
|
||||
Z80_illeg_xDCB_CF:
|
||||
Z80_illeg_xDCB_D0:
|
||||
Z80_illeg_xDCB_D1:
|
||||
Z80_illeg_xDCB_D2:
|
||||
Z80_illeg_xDCB_D3:
|
||||
Z80_illeg_xDCB_D4:
|
||||
Z80_illeg_xDCB_D5:
|
||||
Z80_illeg_xDCB_D7:
|
||||
Z80_illeg_xDCB_D8:
|
||||
Z80_illeg_xDCB_D9:
|
||||
Z80_illeg_xDCB_DA:
|
||||
Z80_illeg_xDCB_DB:
|
||||
Z80_illeg_xDCB_DC:
|
||||
Z80_illeg_xDCB_DD:
|
||||
Z80_illeg_xDCB_DF:
|
||||
Z80_illeg_xDCB_E0:
|
||||
Z80_illeg_xDCB_E1:
|
||||
Z80_illeg_xDCB_E2:
|
||||
Z80_illeg_xDCB_E3:
|
||||
Z80_illeg_xDCB_E4:
|
||||
Z80_illeg_xDCB_E5:
|
||||
Z80_illeg_xDCB_E7:
|
||||
Z80_illeg_xDCB_E8:
|
||||
Z80_illeg_xDCB_E9:
|
||||
Z80_illeg_xDCB_EA:
|
||||
Z80_illeg_xDCB_EB:
|
||||
Z80_illeg_xDCB_EC:
|
||||
Z80_illeg_xDCB_ED:
|
||||
Z80_illeg_xDCB_EF:
|
||||
Z80_illeg_xDCB_F0:
|
||||
Z80_illeg_xDCB_F1:
|
||||
Z80_illeg_xDCB_F2:
|
||||
Z80_illeg_xDCB_F3:
|
||||
Z80_illeg_xDCB_F4:
|
||||
Z80_illeg_xDCB_F5:
|
||||
Z80_illeg_xDCB_F7:
|
||||
Z80_illeg_xDCB_F8:
|
||||
Z80_illeg_xDCB_F9:
|
||||
Z80_illeg_xDCB_FA:
|
||||
Z80_illeg_xDCB_FB:
|
||||
Z80_illeg_xDCB_FC:
|
||||
Z80_illeg_xDCB_FD:
|
||||
Z80_illeg_xDCB_FF:
|
||||
Reference in new issue
Block a user