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remove redundant IEC port write during TX setup

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This commit is contained in:
Paul Gardner-Stephen committed 2019-05-01 22:45:18 +09:30
1 parent 86a579e91c
commit e67eb37937
1 file changed
+4 -5
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c64/kernal/iec_tx_byte.s
+4 -5
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@@ -32,10 +32,6 @@ iec_tx_byte:
;; signal EOI), before asserting CLK again. ;; signal EOI), before asserting CLK again.
jsr iec_wait60us jsr iec_wait60us
;; Re-assert CLK line
jsr iec_assert_clk_release_data
;; Do the actual transmission of 8 bits of data ;; Do the actual transmission of 8 bits of data
ldx #8 ldx #8
@@ -56,7 +52,9 @@ iec_tx_byte_nextbit:
iec_tx_byte_l1: iec_tx_byte_l1:
;; Clock bit out ;; Clock bit out
jsr iec_wait20us jsr iec_wait20us
jsr iec_release_clk jsr iec_release_clk
jsr iec_wait20us jsr iec_wait20us
;; More bits to send? ;; More bits to send?
@@ -64,7 +62,7 @@ iec_tx_byte_l1:
dex dex
bne iec_tx_byte_nextbit bne iec_tx_byte_nextbit
;; Done sending bits. Wait for acknowledgement ;; Done sending bits. Assert CLK and wait for acknowledgement
jsr iec_assert_clk_release_data jsr iec_assert_clk_release_data
;; Acknowledgement must happen within 1ms, else it ;; Acknowledgement must happen within 1ms, else it
@@ -84,5 +82,6 @@ iec_tx_byte_l1:
;; All done. ;; All done.
;; End state is TALKER is asserting CLK, and listener is asserting DATA ;; End state is TALKER is asserting CLK, and listener is asserting DATA
;; until they are ready for the next byte. ;; until they are ready for the next byte.
inc $044f
clc clc
rts rts