diff --git a/src/zvm_m65/z80_instr_block.s b/src/zvm_m65/z80_instr_block.s
index 49e2733f..2028352c 100644
--- a/src/zvm_m65/z80_instr_block.s
+++ b/src/zvm_m65/z80_instr_block.s
@@ -69,3 +69,63 @@ Z80_instr_ED_B8:   ; LDDR
 	dew REG_BC	
 	bne @1
 	jmp ZVM_next
+
+
+!macro Z80_common_CP_block {
+
+	; XXX provide precalculated tables in attic RAM to speed this up
+
+	lda REG_F
+	and #Z80_CF
+	sta REG_F
+	+Z80_PUT_1_NF
+
+	+Z80_FETCH_VIA_HL
+	sta REG_TMP1
+
+	and #$0F                 ; calculate half-carry flag
+	sta REG_TMP2
+	lda REG_A
+	and #$0F
+	sec
+	sbc REG_TMP2
+	and #$F0
+	beq @1
+    +Z80_PUT_1_HF
+@1:	
+	lda REG_A
+	sec
+	sbc REG_TMP1
+	bpl @2
+    +Z80_PUT_1_SF	
+@2:
+	bne @3
+    +Z80_PUT_1_ZF	
+@3:
+	; FALLTROUGH
+}
+
+Z80_instr_ED_A1:   ; CPI
+
+	+Z80_common_CP_block
+	inw REG_HL
+	dew REG_BC
+	+beq ZVM_next
+
+    +Z80_PUT_1_VF
+	jmp ZVM_next
+
+Z80_instr_ED_A9:   ; CPD
+
+	+Z80_common_CP_block
+	dew REG_HL
+	dew REG_BC
+	+beq ZVM_next
+
+    +Z80_PUT_1_VF
+	jmp ZVM_next
+
+Z80_instr_ED_B1:   ; CPIR
+Z80_instr_ED_B9:   ; CPDR
+
+	jmp ZVM_next ; XXX provide implementation
\ No newline at end of file
diff --git a/src/zvm_m65/z80_instr_math_8bit.s b/src/zvm_m65/z80_instr_math_8bit.s
index a7a11f09..dd27c6e1 100644
--- a/src/zvm_m65/z80_instr_math_8bit.s
+++ b/src/zvm_m65/z80_instr_math_8bit.s
@@ -387,7 +387,7 @@ Z80_common_cp:
 	and #%00101000
 	ora z80_ftable_CP, x
 	sta REG_F
-	bvs @V1:
+	bvs @V1
 @V0:
 	bcc @VxC1
 @V0C0:
diff --git a/src/zvm_m65/zvm.s b/src/zvm_m65/zvm.s
index 7afac815..f1b95217 100644
--- a/src/zvm_m65/zvm.s
+++ b/src/zvm_m65/zvm.s
@@ -84,24 +84,6 @@ ZVM: ; entry point
 
 
 
-
-
-;
-; Not implemented yet - XXX implement them!
-;
-
-
-Z80_instr_ED_A1:   ; CPI
-Z80_instr_ED_A9:   ; CPD
-Z80_instr_ED_B1:   ; CPIR
-Z80_instr_ED_B9:   ; CPDR
-
-	jmp ZVM_next ; XXX provide implementation
-
-
-
-
-
 ZVM_memtest:
 
 	; Simple memory test