From ee87f4a775b5fb462714513e41d8c0bfa3716c22 Mon Sep 17 00:00:00 2001 From: Paul Gardner-Stephen Date: Sat, 4 May 2019 22:28:29 +0930 Subject: [PATCH] get to the point of being able to receive some bytes before locking up. --- c64/kernal/iec_rx_byte.s | 22 ++++++++++++---------- c64/kernal/load.s | 2 +- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/c64/kernal/iec_rx_byte.s b/c64/kernal/iec_rx_byte.s index c0db92dc..818f759e 100644 --- a/c64/kernal/iec_rx_byte.s +++ b/c64/kernal/iec_rx_byte.s @@ -58,32 +58,34 @@ iec_rx_clk_wait: iec_rx_bit_loop: - inc $0634 - ;; Wait for CLK to release jsr iec_wait_for_clock_release - inc $0635 - ;; DATA now has the next bit, but inverted. ;; DATA is in bit7, which is a bit annoying. ;; But we can clock it out with a ROL instruction - ;; so that it is in C. We can then ROL it into the - ;; partial data byte + ;; so that it is in C. We can then ROR it into the + ;; partial data byte. + ;; We use ROR so that we shift in from the top, so that + ;; the first bit we shift in ends up in bit 0 after all + ;; 8 bits have been read. + ;; ODD: For some reason we don't need to invert the + ;; received bits. This is weird, because we invert them + ;; on the way out, and everything in the protocol seems + ;; to indicate that we sould do so. But experimentation + ;; has confirmed the bits don't need inversion on reception. + ;; Move data bit into C flag LDA $DD00 ROL ;; Pull it into the data byte pla - ROL - eor #$01 ; Invert the data bit + ROR pha ;; Wait for CLK to re-assert jsr iec_wait_for_clock_assert - inc $0636 - ;; More bits? dex bpl iec_rx_bit_loop diff --git a/c64/kernal/load.s b/c64/kernal/load.s index 5a08c8c5..468dde69 100644 --- a/c64/kernal/load.s +++ b/c64/kernal/load.s @@ -66,7 +66,7 @@ read_loop: ;; Write read data to screen for now inc $ff ldx $ff - sta $0400,x + sta $1000,x plp bcs load_done bcc -