diff --git a/src/zvm_m65/,aliases_zvm.s b/src/zvm_m65/,aliases_zvm.s
index 0fd794b0..dc569d1a 100644
--- a/src/zvm_m65/,aliases_zvm.s
+++ b/src/zvm_m65/,aliases_zvm.s
@@ -39,6 +39,8 @@
 
 !addr REG_TMP1           = $25    ; emulation-specific temporary storage
 !addr REG_TMP2           = $26
+!addr ADDR_IO            = $27    ; 16-bit address for fetching/storing the IO
+
 
 !addr VEC_MOVE_fetch     = $30    ; vector to byte fetch routine, for BIOS routine MOVE
 !addr VEC_MOVE_store     = $32    ; vector to byte store routine, for BIOS routine MOVE
diff --git a/src/zvm_m65/z80_instr_general.s b/src/zvm_m65/z80_instr_general.s
index aca40438..9cae0afa 100644
--- a/src/zvm_m65/z80_instr_general.s
+++ b/src/zvm_m65/z80_instr_general.s
@@ -40,11 +40,12 @@ Z80_instr_37:      ; SCF
 Z80_instr_76:      ; HALT
 
 	; Used to call BIOS routines
+	; XXX probably not the besta idea, GENCPC seems to do some relocations
 
 	ldx #$01 ; default BIOS function, warm start
 
 	lda REG_PC+1
-	cmp #$FE
+	cmp #$FE ;
 	bne @1
 	lda REG_PC+0
 	sec
diff --git a/src/zvm_m65/z80_instr_io.s b/src/zvm_m65/z80_instr_io.s
index fa10ff58..b47beb0b 100644
--- a/src/zvm_m65/z80_instr_io.s
+++ b/src/zvm_m65/z80_instr_io.s
@@ -2,3 +2,80 @@
 ;
 ; Z80 input/output instructions
 ;
+
+
+Z80_instr_DB:                                                                  ; IN A,(n)
+
+	jsr (VEC_fetch_value)
+	sta ADDR_IO+0
+	lda REG_A
+	sta ADDR_IO+1
+	jsr ZVM_fetch_IO
+	sta REG_A
+	jmp ZVM_next
+
+!macro Z80_IN_REGn .REGn {
+	lda REG_C
+	sta ADDR_IO+0
+	lda REG_B
+	sta ADDR_IO+1
+	jsr ZVM_fetch_IO
+	sta .REGn
+	tax
+	lda REG_F
+	and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF)
+	ora z80_ftable_IN_OR_XOR, x
+	sta REG_F
+	jmp ZVM_next
+}
+
+Z80_instr_ED_40:   +Z80_IN_REGn REG_B                                          ; IN B,(C)
+Z80_instr_ED_48:   +Z80_IN_REGn REG_C                                          ; IN C,(C)
+Z80_instr_ED_50:   +Z80_IN_REGn REG_D                                          ; IN D,(C)
+Z80_instr_ED_58:   +Z80_IN_REGn REG_E                                          ; IN E,(C)
+Z80_instr_ED_60:   +Z80_IN_REGn REG_H                                          ; IN H,(C)
+Z80_instr_ED_68:   +Z80_IN_REGn REG_L                                          ; IN L,(C)
+Z80_instr_ED_78:   +Z80_IN_REGn REG_A                                          ; IN A,(C)
+
+Z80_instr_D3:                                                                  ; OUT (n),A
+
+	jsr (VEC_fetch_value)
+	sta ADDR_IO+0
+	lda REG_A
+	sta ADDR_IO+1
+	jsr ZVM_store_IO
+	jmp ZVM_next
+
+Z80_instr_ED_41:                                                               ; OUT (C),B
+
+	lda REG_C
+	sta ADDR_IO+0
+	lda REG_B
+	sta ADDR_IO+1
+	jsr ZVM_store_IO
+	jmp ZVM_next
+
+Z80_instr_ED_49:                                                               ; OUT (C),C
+
+	lda REG_B
+	sta ADDR_IO+1
+	lda REG_C
+	sta ADDR_IO+0
+	jsr ZVM_store_IO
+	jmp ZVM_next
+
+!macro Z80_OUT_REGn .REGn {
+	lda REG_C
+	sta ADDR_IO+0
+	lda REG_B
+	sta ADDR_IO+1
+	lda .REGn 
+	jsr ZVM_store_IO
+	jmp ZVM_next
+}
+
+Z80_instr_ED_51:   +Z80_OUT_REGn REG_D                                         ; OUT (C),D
+Z80_instr_ED_59:   +Z80_OUT_REGn REG_E                                         ; OUT (C),E
+Z80_instr_ED_61:   +Z80_OUT_REGn REG_H                                         ; OUT (C),H
+Z80_instr_ED_69:   +Z80_OUT_REGn REG_L                                         ; OUT (C),L
+Z80_instr_ED_79:   +Z80_OUT_REGn REG_A                                         ; OUT (C),A
diff --git a/src/zvm_m65/z80_instr_math_8bit.s b/src/zvm_m65/z80_instr_math_8bit.s
index f3377cc1..0c3a33f6 100644
--- a/src/zvm_m65/z80_instr_math_8bit.s
+++ b/src/zvm_m65/z80_instr_math_8bit.s
@@ -69,7 +69,7 @@ Z80_instr_FD_A6:   +Z80_AND_VIA_IY_d                                           ;
 !macro Z80_OR_XOR_common_int {
 	lda REG_F
 	and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF - Z80_CF)
-	ora z80_ftable_OR_XOR, x
+	ora z80_ftable_IN_OR_XOR, x
 	sta REG_F
 	jmp ZVM_next
 }
@@ -142,7 +142,7 @@ Z80_instr_FD_B6:   +Z80_OR_VIA_IY_d                                            ;
 	sta REG_A
 	lda REG_F
 	and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF - Z80_CF)
-	ora z80_ftable_OR_XOR
+	ora z80_ftable_IN_OR_XOR
 	sta REG_F
 	jmp ZVM_next
 }
diff --git a/src/zvm_m65/z80_tables.s b/src/zvm_m65/z80_tables.s
index 81c208bd..ea049522 100644
--- a/src/zvm_m65/z80_tables.s
+++ b/src/zvm_m65/z80_tables.s
@@ -25,6 +25,6 @@ z80_ftable_AND:
 
 	+PUT_Z80_FTABLE_AND
 
-z80_ftable_OR_XOR:
+z80_ftable_IN_OR_XOR:
 
-	+PUT_Z80_FTABLE_OR_XOR
+	+PUT_Z80_FTABLE_IN_OR_XOR
diff --git a/src/zvm_m65/zvm_banking.s b/src/zvm_m65/zvm_banking.s
index 99464a3c..d7baa80d 100644
--- a/src/zvm_m65/zvm_banking.s
+++ b/src/zvm_m65/zvm_banking.s
@@ -124,6 +124,20 @@ ZVM_set_bank_1:
 
 	rts
 
+ZVM_fetch_IO:
+
+	; XXX fetch addresses via ADDR_IO - but which ones are safe? Should we have a whitelist?
+	lda #$00
+	sta REG_A
+	rts
+
+ZVM_store_IO:
+
+	; XXX again, we should have a whitelist of addresses
+	rts
+
+
+
 ZVM_fetch_opcode_bank_0:
 
 	; XXX implement, should return byte in .A
diff --git a/src/zvm_m65/zvm_bios.s b/src/zvm_m65/zvm_bios.s
index afd1f441..f0924d6d 100644
--- a/src/zvm_m65/zvm_bios.s
+++ b/src/zvm_m65/zvm_bios.s
@@ -8,8 +8,7 @@
 
 ; $FE00 - $FE63 - jumptable, 3*33 bytes
 ; $FE63 - $FE84 - magic HALT instructions to select BIOS routines
-; $FE85 - $FEFF - unused
-; $FF00 - $FFFF - Disk Drive Tables, dynamically generated, $10 bytes for each one
+; $FE85 - $FFFF - unassigned as of yet
 
 !addr zvm_BIOS_return = Z80_instr_C9 ; RET instruction
 
diff --git a/src/zvm_m65/zvm_core.s b/src/zvm_m65/zvm_core.s
index e71b3775..1e7cbe99 100644
--- a/src/zvm_m65/zvm_core.s
+++ b/src/zvm_m65/zvm_core.s
@@ -169,12 +169,10 @@ Z80_instr_CD:      ; CALL nn
 Z80_instr_CE:      ; ADC A,n
 Z80_instr_CF:      ; RST 08H
 Z80_instr_D0:      ; RET NC
-Z80_instr_D3:      ; OUT (n), A
 Z80_instr_D4:      ; CALL NC,nn
 Z80_instr_D6:      ; SUB n
 Z80_instr_D7:      ; RST 10H
 Z80_instr_D8:      ; RET C
-Z80_instr_DB:      ; IN A,(n)
 Z80_instr_DC:      ; CALL C,nn
 Z80_instr_DE:      ; SBC A,n
 Z80_instr_DF:      ; RST 18H
@@ -277,37 +275,23 @@ Z80_instr_DD_9E:   ; SBC (IX+d)
 Z80_instr_DD_BE:   ; CP (IX+d)
 Z80_instr_DD_E3:   ; EX (SP),IX
 Z80_instr_DD_F9:   ; LD SP,IX
-Z80_instr_ED_40:   ; IN B,(C)
-Z80_instr_ED_41:   ; OUT (C),B
 Z80_instr_ED_42:   ; SBC HL,BC
 Z80_instr_ED_43:   ; LD (nn),BC
 Z80_instr_ED_44:   ; NEG
 Z80_instr_ED_45:   ; RETN
-Z80_instr_ED_48:   ; IN C,(C)
-Z80_instr_ED_49:   ; OUT (C),C
 Z80_instr_ED_4A:   ; ADC HL,BC
 Z80_instr_ED_4B:   ; LD BC,(nn)
 Z80_instr_ED_4D:   ; RETTI
-Z80_instr_ED_50:   ; IN D,(C)
-Z80_instr_ED_51:   ; OUT (C),D
 Z80_instr_ED_52:   ; SBC HL,DE
 Z80_instr_ED_53:   ; LD (nn),DE
-Z80_instr_ED_58:   ; IN E,(C)
-Z80_instr_ED_59:   ; OUT (C),E
 Z80_instr_ED_5A:   ; ADC HL,DE
 Z80_instr_ED_5B:   ; LD DE,(nn)
-Z80_instr_ED_60:   ; IN H,(C)
-Z80_instr_ED_61:   ; OUT (C),H
 Z80_instr_ED_62:   ; SBC HL,HL
 Z80_instr_ED_67:   ; RRD
-Z80_instr_ED_68:   ; IN L,(C)
-Z80_instr_ED_69:   ; OUT (C),L
 Z80_instr_ED_6A:   ; ADC HL,HL
 Z80_instr_ED_6F:   ; RLD
 Z80_instr_ED_72:   ; SBC HL,SP
 Z80_instr_ED_73:   ; LD (nn),SP
-Z80_instr_ED_78:   ; IN A,(C)
-Z80_instr_ED_79:   ; OUT (C),A
 Z80_instr_ED_7A:   ; ADC HL,SP
 Z80_instr_ED_7B:   ; LD SP,(nn)
 Z80_instr_ED_A0:   ; LDI
diff --git a/tools/generate_z80_tables.cc b/tools/generate_z80_tables.cc
index 91c01d0b..df0ee434 100644
--- a/tools/generate_z80_tables.cc
+++ b/tools/generate_z80_tables.cc
@@ -193,10 +193,10 @@ std::string generateAndTable(void)
 	return outStr.str() + "}\n\n\n";
 }
 
-std::string generateOrXorTable(void)
+std::string generateInOrXorTable(void)
 {
 	std::stringstream outStr;
-	outStr << "!macro PUT_Z80_FTABLE_OR_XOR {\n";
+	outStr << "!macro PUT_Z80_FTABLE_IN_OR_XOR {\n";
 
 	for (uint16_t idx = 0; idx < 0x100; idx++)
 	{
@@ -244,7 +244,7 @@ void writeTables()
 	outFile << generateIncTable();
 	outFile << generateDecTable();
 	outFile << generateAndTable();
-	outFile << generateOrXorTable();
+	outFile << generateInOrXorTable();
 	outFile << generateDaaTables();
 
 	// XXX