generally remove some debug output, add missing file, and make KERNAL LOAD routine more complete.

This commit is contained in:
Paul Gardner-Stephen committed 2019-05-04 23:12:54 +09:30
1 parent d124349e50
commit fa55c83fff
8 files changed
+162 -31

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@@ -5,19 +5,13 @@
iec_rx_byte:
inc $062f
;; First, we wait for the talker to release the CLK line.
jsr iec_wait_for_clock_release
inc $0630
;; We then release the data line
;; (We can use this routine, since we weren't holding CLK, anyway)
jsr iec_release_clk_and_data
inc $0631
;; Wait for talker to assert CLK.
;; If >200usec, then it is EOI and we have to assert the
;; DATA line for 60 usec to tell the TALKER that we have
@@ -99,8 +93,6 @@ iec_rx_bit_loop:
dex
bpl iec_rx_bit_loop
inc $0637
;; Then we must within 1000usec acknowledge the frame by
;; asserting DATA. At this point, CLK is asserted by the
;; talker and DATA by us, i.e., we are ready to receive