generally remove some debug output, add missing file, and make KERNAL LOAD routine more complete.
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@@ -5,19 +5,13 @@
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iec_rx_byte:
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inc $062f
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;; First, we wait for the talker to release the CLK line.
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jsr iec_wait_for_clock_release
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inc $0630
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;; We then release the data line
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;; (We can use this routine, since we weren't holding CLK, anyway)
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jsr iec_release_clk_and_data
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inc $0631
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;; Wait for talker to assert CLK.
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;; If >200usec, then it is EOI and we have to assert the
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;; DATA line for 60 usec to tell the TALKER that we have
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@@ -99,8 +93,6 @@ iec_rx_bit_loop:
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dex
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bpl iec_rx_bit_loop
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inc $0637
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;; Then we must within 1000usec acknowledge the frame by
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;; asserting DATA. At this point, CLK is asserted by the
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;; talker and DATA by us, i.e., we are ready to receive
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