;; #LAYOUT# STD *        #TAKE
;; #LAYOUT# CRT KERNAL_0 #TAKE
;; #LAYOUT# M65 KERNAL_1 #TAKE
;; #LAYOUT# *   *        #IGNORE

; Not on a Blade, which has no VIC-II
!ifndef CONFIG_ARNITECH_BLADE {

;
; The VIC-II set-up of vicii_init (e5a0.vicii_init.s), moved out of $E5A0-$E5C8
; so that $E5B4 is free
;


vicii_init_registers:

	; Clear everything - turn off sprites (observed hanging around after
 	; running programs and resetting), etc.

	lda #$00
 	ldx #$2E
@1:
 	sta __VIC_BASE, x
 	dex
 	bpl @1

	; Set up default IO values
	; - [CM64] page 129       - VIC_SCROLY
	; - [CM64] pages 140-144  - VIC_SCROLX
	; - [CM64] pages 145-146  - VIC_YMCSB

	lda #$1B                           ; according to [CM64] page 137 some software assumes oldest bit is 0
	sta VIC_SCROLY
	lda #$C8
	sta VIC_SCROLX                     ; 40 column, etc.
	lda #$14
	sta VIC_YMCSB
	lda #$0F
	sta VIC_IRQ                        ; clear all interrupts

	; We use a different colour scheme of white text on all blue by default,
	; but brand-specific color scheme can also be enabled

	lda #CONFIG_COLOR_BG
	sta VIC_EXTCOL
	sta VIC_BGCOL0

	; Setup default I/O devices

!ifdef CONFIG_IEC {
	jmp clrchn_reset
} else {
	jmp CLRCHN
}

} ; CONFIG_ARNITECH_BLADE