110 lines
2.8 KiB
ArmAsm
110 lines
2.8 KiB
ArmAsm
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;
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; Z80 input/output instructions
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;
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; XXX ZVM_store_IO should go to next instruction
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Z80_instr_DB: ; IN A,(n)
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jsr (VEC_fetch_via_PC_inc)
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sta ADDR_IO+0
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lda REG_A
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sta ADDR_IO+1
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jsr ZVM_fetch_IO
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sta REG_A
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jmp ZVM_next
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!macro Z80_IN_REGn .REGn {
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lda REG_C
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sta ADDR_IO+0
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lda REG_B
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sta ADDR_IO+1
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jsr ZVM_fetch_IO
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sta .REGn
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tax
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lda REG_F
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and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF - Z80_XF - Z80_YF)
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ora z80_ftable_IN_OR_XOR, x
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sta REG_F
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jmp ZVM_next
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}
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!macro Z80_IN_NULL {
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lda REG_C
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sta ADDR_IO+0
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lda REG_B
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sta ADDR_IO+1
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jsr ZVM_fetch_IO
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tax
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lda REG_F
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and #($FF - Z80_SF - Z80_ZF - Z80_HF - Z80_PF - Z80_NF - Z80_XF - Z80_YF)
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ora z80_ftable_IN_OR_XOR, x
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sta REG_F
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jmp ZVM_next
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}
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Z80_instr_ED_40: +Z80_IN_REGn REG_B ; IN B,(C)
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Z80_instr_ED_48: +Z80_IN_REGn REG_C ; IN C,(C)
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Z80_instr_ED_50: +Z80_IN_REGn REG_D ; IN D,(C)
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Z80_instr_ED_58: +Z80_IN_REGn REG_E ; IN E,(C)
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Z80_instr_ED_60: +Z80_IN_REGn REG_H ; IN H,(C)
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Z80_instr_ED_68: +Z80_IN_REGn REG_L ; IN L,(C)
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Z80_instr_ED_78: +Z80_IN_REGn REG_A ; IN A,(C)
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Z80_illeg_ED_70: +Z80_IN_NULL ; IN (C)
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Z80_instr_D3: ; OUT (n),A
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jsr (VEC_fetch_via_PC_inc)
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sta ADDR_IO+0
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lda REG_A
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sta ADDR_IO+1
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jsr ZVM_store_IO
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jmp ZVM_next
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Z80_instr_ED_41: ; OUT (C),B
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lda REG_C
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sta ADDR_IO+0
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lda REG_B
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sta ADDR_IO+1
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jsr ZVM_store_IO
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jmp ZVM_next
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Z80_instr_ED_49: ; OUT (C),C
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lda REG_B
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sta ADDR_IO+1
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lda REG_C
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sta ADDR_IO+0
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jsr ZVM_store_IO
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jmp ZVM_next
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!macro Z80_OUT_REGn .REGn {
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lda REG_C
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sta ADDR_IO+0
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lda REG_B
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sta ADDR_IO+1
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lda .REGn
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jsr ZVM_store_IO
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jmp ZVM_next
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}
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!macro Z80_OUT_NULL {
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lda REG_C
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sta ADDR_IO+0
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lda REG_B
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sta ADDR_IO+1
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lda #$00
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jsr ZVM_store_IO
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jmp ZVM_next
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}
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Z80_instr_ED_51: +Z80_OUT_REGn REG_D ; OUT (C),D
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Z80_instr_ED_59: +Z80_OUT_REGn REG_E ; OUT (C),E
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Z80_instr_ED_61: +Z80_OUT_REGn REG_H ; OUT (C),H
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Z80_instr_ED_69: +Z80_OUT_REGn REG_L ; OUT (C),L
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Z80_instr_ED_79: +Z80_OUT_REGn REG_A ; OUT (C),A
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Z80_illeg_ED_71: +Z80_OUT_NULL ; OUT (C),0
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