102 lines
4.3 KiB
ArmAsm
102 lines
4.3 KiB
ArmAsm
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;
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; Z80 instruction dispatchers
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;
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!macro ZVM_DISPATCH .TAB_LO, .TAB_HI {
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; Fetch and execute next opcode
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+Z80_FETCH_VIA_PC_INC
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asl
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tax
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bcs @1
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jmp (.TAB_LO,x) ; execute opcode $00-$7F
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@1: jmp (.TAB_HI,x) ; execute opcode $80-$FF
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}
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ZVM_store_via_HL_next:
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+Z80_STORE_BACK_VIA_HL
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; FALLTROUGH
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; unsupported illegal instructions
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Z80_unsupported:
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; XXX add a separate handler to warn about illegal instructions
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; block I/O transfer - not implemented for now XXX implement them
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Z80_instr_ED_A2: ; INI
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Z80_instr_ED_B2: ; INIR
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Z80_instr_ED_AA: ; IND
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Z80_instr_ED_BA: ; INDR
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Z80_instr_ED_A3: ; OUTI
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Z80_instr_ED_B3: ; OTIR
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Z80_instr_ED_AB: ; OUTD
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Z80_instr_ED_BB: ; OTDR
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; XXX add a separate handler to warn about them
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; LD instructions with no effect
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Z80_instr_40: ; LD B,B
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Z80_instr_49: ; LD C,C
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Z80_instr_52: ; LD D,D
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Z80_instr_5B: ; LD E,E
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Z80_instr_64: ; LD H,H
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Z80_instr_6D: ; LD L,L
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Z80_instr_7F: ; LD A,A
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Z80_illeg_DD_64: ; LD IXH,IXH
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Z80_illeg_DD_6D: ; LD IXL,IXL
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Z80_illeg_FD_64: ; LD IYH,IYH
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Z80_illeg_FD_6D: ; LD IYL,IYL
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; Instructions needed only for interrupts (emulation not needed for CP/M)
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Z80_instr_ED_46: ; IM 0
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Z80_illeg_ED_4E: ; IM 0
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Z80_illeg_ED_66: ; IM 0
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Z80_illeg_ED_6E: ; IM 0
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Z80_instr_ED_56: ; IM 1
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Z80_illeg_ED_76: ; IM 1
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Z80_instr_ED_5E: ; IM 2
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Z80_illeg_ED_7E: ; IM 2
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; NOP
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Z80_instr_00: ; NOP
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Z80_illeg_ED_77: ; NOP
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Z80_illeg_ED_7F: ; NOP
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; Fetch and execute the next instruction
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ZVM_next: +ZVM_DISPATCH Z80_vectab_0, Z80_vectab_1
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; Dispatch via jumptable
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Z80_instr_CB: +ZVM_DISPATCH Z80_vectab_CB_0, Z80_vectab_CB_1 ; #CB
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Z80_instr_DD: +ZVM_DISPATCH Z80_vectab_DD_0, Z80_vectab_DD_1 ; #DD
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Z80_instr_ED: +ZVM_DISPATCH Z80_vectab_ED_0, Z80_vectab_ED_1 ; #ED
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Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ; #FD
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!macro ZVM_DISPATCH_REG_IXY .REG_nn {
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; XXX is the displacement calculated correctly?
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; Fetch value from IX/IY, subtract 128
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lda .REG_nn+1
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sta PTR_IXY_d+1
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lda .REG_nn+0
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bmi @1
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dec PTR_IXY_d+1
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@1:
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eor #%10000000
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sta PTR_IXY_d+0
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+Z80_FETCH_VIA_PC_INC
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tax
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lda z80_otable_displacement,x
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clc
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adc REG_PC+0
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sta REG_PC+0
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bcc @2
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inc REG_PC+1
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@2:
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+ZVM_DISPATCH Z80_vectab_xDCB_0, Z80_vectab_xDCB_1
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}
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Z80_instr_DD_CB: +ZVM_DISPATCH_REG_IXY REG_IX ; #DDCB
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Z80_instr_FD_CB: +ZVM_DISPATCH_REG_IXY REG_IY ; #FDCB
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