164 lines
2.0 KiB
ArmAsm
164 lines
2.0 KiB
ArmAsm
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;
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; Z80 block processing and search instructions
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;
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Z80_instr_ED_A0: ; LDI
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lda REG_F
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and #($FF - Z80_HF - Z80_PF - Z80_NF)
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sta REG_F
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+Z80_FETCH_VIA_HL
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+Z80_STORE_VIA_DE
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inw REG_HL
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inw REG_DE
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dew REG_BC
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+beq ZVM_next
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+Z80_PUT_1_VF
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jmp ZVM_next
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Z80_instr_ED_B0: ; LDIR
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lda REG_F
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and #($FF - Z80_HF - Z80_PF - Z80_NF)
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sta REG_F
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@1:
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+Z80_FETCH_VIA_HL
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+Z80_STORE_VIA_DE
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inw REG_HL
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inw REG_DE
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dew REG_BC
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bne @1
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jmp ZVM_next
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Z80_instr_ED_A8: ; LDD
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lda REG_F
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and #($FF - Z80_HF - Z80_PF - Z80_NF)
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sta REG_F
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+Z80_FETCH_VIA_HL
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+Z80_STORE_VIA_DE
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dew REG_HL
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dew REG_DE
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dew REG_BC
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+beq ZVM_next
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+Z80_PUT_1_VF
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jmp ZVM_next
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Z80_instr_ED_B8: ; LDDR
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lda REG_F
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and #($FF - Z80_HF - Z80_PF - Z80_NF)
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sta REG_F
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@1:
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+Z80_FETCH_VIA_HL
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+Z80_STORE_VIA_DE
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dew REG_HL
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dew REG_DE
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dew REG_BC
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bne @1
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jmp ZVM_next
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!macro Z80_common_CP_block {
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; XXX provide precalculated tables in attic RAM to speed this up
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lda REG_F
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and #Z80_CF
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sta REG_F
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+Z80_PUT_1_NF
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+Z80_FETCH_VIA_HL
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sta REG_TMP1
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and #$0F ; calculate half-carry flag
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sta REG_TMP2
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lda REG_A
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and #$0F
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sec
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sbc REG_TMP2
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and #$F0
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beq @1
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+Z80_PUT_1_HF
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@1:
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lda REG_A
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sec
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sbc REG_TMP1
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bpl @2
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+Z80_PUT_1_SF
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@2:
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bne @3
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+Z80_PUT_1_ZF
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@3:
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; FALLTROUGH
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}
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Z80_instr_ED_A1: ; CPI
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+Z80_common_CP_block
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inw REG_HL
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dew REG_BC
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+beq ZVM_next
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+Z80_PUT_1_VF
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jmp ZVM_next
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Z80_instr_ED_A9: ; CPD
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+Z80_common_CP_block
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dew REG_HL
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dew REG_BC
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+beq ZVM_next
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+Z80_PUT_1_VF
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jmp ZVM_next
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Z80_instr_ED_B1: ; CPIR
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+Z80_common_CP_block
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inw REG_HL
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dew REG_BC
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beq Z80_common_CPIR_CPDR
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+Z80_FETCH_VIA_HL
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cmp REG_A
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bne Z80_instr_ED_B1
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+Z80_PUT_1_VF
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jmp ZVM_next
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Z80_common_CPIR_CPDR:
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+Z80_FETCH_VIA_HL
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cmp REG_A
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+bne ZVM_next
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+Z80_PUT_1_VF
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jmp ZVM_next
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Z80_instr_ED_B9: ; CPDR
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+Z80_common_CP_block
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dew REG_HL
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dew REG_BC
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beq Z80_common_CPIR_CPDR
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+Z80_FETCH_VIA_HL
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cmp REG_A
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bne Z80_instr_ED_B9
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+Z80_PUT_1_VF
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jmp ZVM_next
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