124 lines
3.5 KiB
ArmAsm
124 lines
3.5 KiB
ArmAsm
;; Receive a byte from the IEC bus.
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;; Implemented based on https://www.pagetable.com/?p=1135, https://github.com/mist64/cbmbus_doc,
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;; http://www.zimmers.net/anonftp/pub/cbm/programming/serial-bus.pdf (page 11)
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iec_rx_byte:
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;; Timing is critical here - execute on disabled IRQs
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php
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sei
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;; First, we wait for the talker to release the CLK line
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jsr iec_wait_for_clk_release
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;; We then release the DATA to signal we are ready
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;; We can use this routine, since we weren't pulling CLK anyway
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jsr iec_release_clk_data
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;; Wait till data line is released (someone else might be holding it)
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jsr iec_wait_for_data_release
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;; Wait for talker to pull CLK.
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;; If over 200 usec (205 cycles on NTSC machine) , then it is EOI.
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;; Loop iteraction takes 13 cycles, 17 full iterations are enough
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ldx #$11 ; 2 cycles
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iec_rx_clk_wait1:
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lda CI2PRA ; 4 cycles
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rol ; 2 cycles, to put BIT_CI2PRA_CLK_IN as the last bit
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bpl iec_rx_not_eoi ; 2 cycles if not jumped
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dex ; 2 cycles
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bne iec_rx_clk_wait1 ; 3 cycles if jumped
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;; Timeout - either this is the last byte of stream, or the stream is empty at all.
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;; Mark end of stream in IOSTATUS
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jsr kernalstatus_EOI
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iec_rx_not_empty:
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;; Pull data for 60 usec to confirm it
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jsr iec_release_clk_pull_data
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jsr iec_wait60us
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jsr iec_release_clk_data
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iec_rx_not_eoi:
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;; Latch input bits in on rising edge of CLK, eight times for eight bits.
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ldx #7
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;; Get empty byte to load into.
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lda #$00
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pha
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iec_rx_bit_loop:
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;; Wait for CLK to release
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jsr iec_wait_for_clk_release
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;; (we do this implicitly below, with a tighter routine,
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;; so that we don't have timing problems, as the requirements
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;; are quite tight. Basically we need to read the clock and data
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;; bit from the same byte read.
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;; DATA now has the next bit, but inverted (well, except that it turns out not to be).
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;; DATA is in bit 7, which is a bit annoying.
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;; But we can clock it out with a ROL instruction
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;; so that it is in C. We can then ROR it into the
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;; partial data byte.
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;; We use ROR so that we shift in from the top, so that
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;; the first bit we shift in ends up in bit 0 after all
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;; 8 bits have been read.
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;; ODD: For some reason we don't need to invert the
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;; received bits. This is weird, because we invert them
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;; on the way out, and everything in the protocol seems
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;; to indicate that we sould do so. But experimentation
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;; has confirmed the bits don't need inversion on reception.
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;; Move data bit into C flag, and loop until bit 6 clears
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;; i.e., the clock has been released.
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* lda CI2PRA
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rol
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bpl -
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;; Pull it into the data byte
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pla
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ror
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pha
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;; Wait for CLK to be pulled again, over 300 usec (307 cycles on NTSC)
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;; consider this a timeout
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ldy #$19 ; 2 cycles
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iec_rx_clk_wait2:
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lda CI2PRA ; 4 cycles
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rol ; 2 cycles, to put BIT_CI2PRA_CLK_IN as the last bit
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bpl + ; 2 cycles if not jumped
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dey ; 2 cycles
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bne iec_rx_clk_wait2 ; 3 cycles if jumped
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;; Timeout
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jsr kernalstatus_EOI
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pla
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plp
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sec ; XXX confirm that sec is really a way to report timeout here
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rts
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*
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;; More bits?
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dex
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bpl iec_rx_bit_loop
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;; Then we must within 1000 usec acknowledge the frame by
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;; pulling DATA. At this point, CLK is pulled by the
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;; talker and DATA by us, i.e., we are ready to receive
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;; the next byte. (p11).
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jsr iec_release_clk_pull_data
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;; Retreive the received byte
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pla
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;; Return no-error
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plp
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clc
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rts
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