151 lines
2.5 KiB
ArmAsm
151 lines
2.5 KiB
ArmAsm
// #LAYOUT# STD * #TAKE
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// #LAYOUT# * BASIC_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// Math package - multiplies FAC1 by FAC2
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//
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// Input:
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// - .A - must load FAC1 exponent ($61) beforehand to set the zero flag
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//
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// Note:
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// - load FAC2 after FAC1, or mimic the Kernals sign comparison (XXX do we need it?)
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//
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// See also:
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// - [CM64] Computes Mapping the Commodore 64 - page 113 XXX address does not match
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// - https://www.c64-wiki.com/wiki/Floating_point_arithmetic
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// - https://codebase64.org/doku.php?id=base:kernal_floating_point_mathematics
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//
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// XXX provide implementation
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mul_FAC2_FAC1:
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// First handle special case of multiplying by 0
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lda FAC1_exponent
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beq mul_FAC2_FAC1_done
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lda FAC2_exponent
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bne !+
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sta FAC1_exponent
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beq mul_FAC2_FAC1_done
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!:
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// Multiply signs
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lda FAC1_sign
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eor FAC2_sign
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sta FAC1_sign
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// Check if exponents can be added without overflow/underflow
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lda FAC1_exponent
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and #$80
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eor FAC2_exponent
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bmi mul_FAC2_FAC1_add_exponents // exponent signs are opposite, we can add them safely
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// Both exponents are either negative (below $80), or both are non-negative ($80 or above),
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// try to add them
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lda FAC1_exponent
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clc
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adc FAC2_exponent
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bpl mul_FAC2_FAC1_sub_exp_bias // branch if we can add values
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// We cannot add them, result would over/underflow; set result as
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// either 0 or maximum possible float
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lda FAC1_exponent
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bmi_16 set_FAC1_max
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lda #$00
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sta FAC1_exponent
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rts
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mul_FAC2_FAC1_add_exponents:
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// Add the exponents
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lda FAC1_exponent
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clc
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adc FAC2_exponent
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// FALLTROUGH
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mul_FAC2_FAC1_sub_exp_bias:
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sec
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sbc #$80 // bias
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sta FAC1_exponent
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// Multiply the mantissas
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// XXX
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STUB_IMPLEMENTATION()
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mul_FAC2_FAC1_done:
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rts
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mul_8x8: // XXX we should probably move this subroutine to separate file
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// Routine based on code by djmips, taken from:
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// - https://codebase64.org/doku.php?id=base:8bit_multiplication_16bit_product_fast_no_tables
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//
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// input: mul1, mul2
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// optput: .A (high byte), mul1 (low byte)
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.label mul1 = INDEX+2
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.label mul2 = INDEX+3
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lda #$00
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dec mul2 // decrement because we will be adding with carry set for speed (an extra one)
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ror mul1
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bcc !+
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adc mul2
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!:
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ror
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ror mul1
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bcc !+
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adc mul2
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!:
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ror
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ror mul1
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bcc !+
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adc mul2
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!:
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ror
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ror mul1
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bcc !+
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adc mul2
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!:
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ror
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ror mul1
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bcc !+
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adc mul2
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!:
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ror
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ror mul1
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bcc !+
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adc mul2
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!:
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ror
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ror mul1
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bcc !+
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adc mul2
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!:
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ror
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ror mul1
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bcc !+
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adc mul2
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!:
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ror
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ror mul1
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inc mul2
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rts
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