414 lines
4.5 KiB
ArmAsm
414 lines
4.5 KiB
ArmAsm
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;
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; Z80 data load instructions, 8 bit
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;
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;
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; load register with other register
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;
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Z80_instr_41: ; LD B,C
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lda REG_C
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sta REG_B
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rts
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Z80_instr_42: ; LD B,D
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lda REG_D
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sta REG_B
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rts
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Z80_instr_43: ; LD B,E
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lda REG_E
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sta REG_B
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rts
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Z80_instr_44: ; LD B,H
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lda REG_H
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sta REG_B
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rts
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Z80_instr_45: ; LD B,L
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lda REG_L
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sta REG_B
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rts
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Z80_instr_47: ; LD B,A
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lda REG_A
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sta REG_B
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rts
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Z80_instr_48: ; LD C,B
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lda REG_B
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sta REG_C
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rts
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Z80_instr_4A: ; LD C,D
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lda REG_D
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sta REG_C
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rts
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Z80_instr_4B: ; LD C,E
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lda REG_E
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sta REG_C
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rts
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Z80_instr_4C: ; LD C,H
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lda REG_H
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sta REG_C
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rts
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Z80_instr_4D: ; LD C,L
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lda REG_L
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sta REG_C
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rts
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Z80_instr_4F: ; LD C,A
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lda REG_A
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sta REG_C
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rts
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Z80_instr_50: ; LD D,B
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lda REG_B
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sta REG_D
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rts
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Z80_instr_51: ; LD D,C
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lda REG_C
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sta REG_D
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rts
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Z80_instr_53: ; LD D,E
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lda REG_E
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sta REG_D
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rts
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Z80_instr_54: ; LD D,H
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lda REG_H
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sta REG_D
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rts
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Z80_instr_55: ; LD D,L
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lda REG_L
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sta REG_D
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rts
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Z80_instr_57: ; LD D,A
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lda REG_A
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sta REG_D
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rts
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Z80_instr_58: ; LD E,B
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lda REG_B
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sta REG_E
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rts
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Z80_instr_59: ; LD E,C
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lda REG_C
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sta REG_E
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rts
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Z80_instr_5A: ; LD E,D
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lda REG_D
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sta REG_E
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rts
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Z80_instr_5C: ; LD E,H
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lda REG_H
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sta REG_E
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rts
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Z80_instr_5D: ; LD E,L
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lda REG_L
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sta REG_E
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rts
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Z80_instr_5F: ; LD E,A
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lda REG_A
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sta REG_E
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rts
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Z80_instr_60: ; LD H,B
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lda REG_B
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sta REG_H
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rts
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Z80_instr_61: ; LD H,C
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lda REG_C
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sta REG_H
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rts
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Z80_instr_62: ; LD H,D
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lda REG_D
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sta REG_H
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rts
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Z80_instr_63: ; LD H,E
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lda REG_E
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sta REG_H
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rts
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Z80_instr_65: ; LD H,L
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lda REG_L
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sta REG_H
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rts
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Z80_instr_67: ; LD H,A
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lda REG_A
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sta REG_H
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rts
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Z80_instr_68: ; LD L,B
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lda REG_B
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sta REG_L
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rts
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Z80_instr_69: ; LD L,C
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lda REG_C
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sta REG_L
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rts
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Z80_instr_6A: ; LD L,D
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lda REG_D
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sta REG_L
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rts
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Z80_instr_6B: ; LD L,E
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lda REG_E
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sta REG_L
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rts
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Z80_instr_6C: ; LD L,H
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lda REG_H
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sta REG_L
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rts
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Z80_instr_6F: ; LD L,A
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lda REG_A
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sta REG_L
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rts
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Z80_instr_78: ; LD A,B
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lda REG_B
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sta REG_A
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rts
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Z80_instr_79: ; LD A,C
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lda REG_C
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sta REG_A
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rts
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Z80_instr_7A: ; LD A,D
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lda REG_D
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sta REG_A
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rts
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Z80_instr_7B: ; LD A,E
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lda REG_E
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sta REG_A
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rts
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Z80_instr_7C: ; LD A,H
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lda REG_H
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sta REG_A
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rts
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Z80_instr_7D: ; LD A,L
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lda REG_L
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sta REG_A
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rts
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;
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; load register with immediate value
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;
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Z80_instr_06: ; LD B,n
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jsr VEC_fetch_value
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sta REG_B
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rts
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Z80_instr_0E: ; LD C,n
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jsr VEC_fetch_value
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sta REG_C
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rts
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Z80_instr_16: ; LD D,n
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jsr VEC_fetch_value
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sta REG_D
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rts
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Z80_instr_1E: ; LD E,n
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jsr VEC_fetch_value
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sta REG_E
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rts
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Z80_instr_26: ; LD H,n
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jsr VEC_fetch_value
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sta REG_H
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rts
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Z80_instr_2E: ; LD L,n
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jsr VEC_fetch_value
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sta REG_L
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rts
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Z80_instr_3E: ; LD A,n
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jsr VEC_fetch_value
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sta REG_A
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rts
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;
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; load register with memory content (via HL)
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;
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Z80_instr_46: ; LD B,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_B
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rts
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Z80_instr_4E: ; LD C,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_C
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rts
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Z80_instr_56: ; LD D,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_D
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rts
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Z80_instr_5E: ; LD E,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_E
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rts
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Z80_instr_66: ; LD H,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_H
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rts
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Z80_instr_6E: ; LD L,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_L
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rts
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Z80_instr_7E: ; LD A,(HL)
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jsr (VEC_fetch_via_HL)
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sta REG_A
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rts
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; XXX put here LD r,(IX+d) family
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; XXX put here LD r,(IY+d) family
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;
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; load memory content (via HL) with register
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;
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Z80_instr_70: ; LD (HL),B
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lda REG_B
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jmp (VEC_store_via_HL)
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Z80_instr_71: ; LD (HL),C
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lda REG_C
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jmp (VEC_store_via_HL)
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Z80_instr_72: ; LD (HL),D
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lda REG_D
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jmp (VEC_store_via_HL)
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Z80_instr_73: ; LD (HL),E
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lda REG_E
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jmp (VEC_store_via_HL)
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Z80_instr_74: ; LD (HL),H
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lda REG_H
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jmp (VEC_store_via_HL)
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Z80_instr_75: ; LD (HL),L
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lda REG_L
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jmp (VEC_store_via_HL)
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Z80_instr_77: ; LD (HL),A
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lda REG_A
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jmp (VEC_store_via_HL)
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; XXX put here LD (IX+d),r family
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; XXX put here LD (IY+d),r family
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;
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; load memory content (via HL) with immediate value
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;
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Z80_instr_36: ; LD (HL),n
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jsr VEC_fetch_value
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jmp (VEC_store_via_HL)
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; XXX put here LD (IX+d),n family
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; XXX put here LD (IY+d),n family
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; XXX put here LD A,(BC) / LD A,(DE) / LD A,(nn) / LD (BC), A / LD (DE),A / LD (nn),A
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; XXX put here LD A,I / LD A,R
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; XXX put here LD I,A / LD R,A
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