499 lines
16 KiB
ArmAsm
499 lines
16 KiB
ArmAsm
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;
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; Z80 Virtual Machine core routines
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;
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ZVM_entry:
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; Reset stack pointer - this routine will never return
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ldx #$FF
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txs
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; Skip the IRQ processing, even if Kernal reenables it
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sei
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lda #<return_from_interrupt
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sta CINV+0
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lda #>return_from_interrupt
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sta CINV+1
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; Make sure $C000-$CFFF ROM is mapped-in, we keep our proxies there
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lda VIC_CTRLA
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ora #%00100000
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sta VIC_CTRLA
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; Setup colours, print welcome message
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lda #$00
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sta VIC_EXTCOL
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sta VIC_BGCOL0
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jsr PRIMM
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!byte KEY_GREEN, KEY_ESC, 'o', KEY_CLR, KEY_C65_SHIFT_ON, KEY_TXT, KEY_C65_SHIFT_OFF
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!pet "Open ROMs MEGA65 BIOS for CP/M", $0D
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!pet "Zilog Z80 to 45GS02 translator", $0D
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!byte $0D,$0D
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!byte 0
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; XXX code is not ready to progress further
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jsr PRIMM
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!byte $0D
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!pet "* Implementation not finished yet - system HALTED *"
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!byte 0
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@1
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bra @1
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jmp zvm_BIOS_00_BOOT
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ZVM_store_next:
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sta [PTR_DATA],z
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; FALLTROUGH
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!macro ZVM_DISPATCH .TAB_LO, .TAB_HI {
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; Fetch and execute next opcode
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jsr (VEC_fetch_value)
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asl
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tax
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bcs @1
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jmp (.TAB_LO,x) ; execute opcode $00-$7F
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@1: jmp (.TAB_HI,x) ; execute opcode $80-$FF
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}
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; unsupported illegal instructions
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Z80_unsupported:
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; XXX add a separate handler for illegal instructions
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; LD instructions with no effect
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Z80_instr_40: ; LD B,B
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Z80_instr_49: ; LD C,C
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Z80_instr_52: ; LD D,D
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Z80_instr_5B: ; LD E,E
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Z80_instr_64: ; LD H,H
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Z80_instr_6D: ; LD L,L
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Z80_instr_7F: ; LD A,A
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Z80_illeg_DD_64: ; LD IXH,IXH
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Z80_illeg_DD_6D: ; LD IXL,IXL
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Z80_illeg_FD_64: ; LD IYH,IYH
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Z80_illeg_FD_6D: ; LD IYL,IYL
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; For interrupts (emulation not needed for CP/M)
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Z80_instr_ED_46: ; IM 0
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Z80_illeg_ED_4E: ; IM 0
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Z80_illeg_ED_66: ; IM 0
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Z80_illeg_ED_6E: ; IM 0
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Z80_instr_ED_56: ; IM 1
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Z80_illeg_ED_76: ; IM 1
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Z80_instr_ED_5E: ; IM 2
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Z80_illeg_ED_7E: ; IM 2
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; Real NOP
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Z80_instr_00: ; NOP
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Z80_illeg_ED_77: ; NOP
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Z80_illeg_ED_7F: ; NOP
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; Dispatch via jumptable
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ZVM_next: +ZVM_DISPATCH Z80_vectab_0, Z80_vectab_1
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Z80_instr_CB: +ZVM_DISPATCH Z80_vectab_CB_0, Z80_vectab_CB_1 ; #CB
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Z80_instr_DD: +ZVM_DISPATCH Z80_vectab_DD_0, Z80_vectab_DD_1 ; #DD
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Z80_instr_ED: +ZVM_DISPATCH Z80_vectab_ED_0, Z80_vectab_ED_1 ; #ED
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Z80_instr_FD: +ZVM_DISPATCH Z80_vectab_FD_0, Z80_vectab_FD_1 ; #FD
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;
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; Not implemented yet - XXX implement them!
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;
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Z80_instr_DD_CB: ; #DDCB
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Z80_instr_FD_CB: ; #FDCB
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Z80_instr_09: ; ADD HL,BC
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Z80_instr_19: ; ADD HL,DE
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Z80_instr_22: ; LD (nn),HL
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Z80_instr_29: ; ADD HL,HL
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Z80_instr_2A: ; LD HL,(nn)
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Z80_instr_39: ; ADD HL,SP
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Z80_instr_80: ; ADD A,B
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Z80_instr_81: ; ADD A,C
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Z80_instr_82: ; ADD A,D
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Z80_instr_83: ; ADD A,E
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Z80_instr_84: ; ADD A,H
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Z80_instr_85: ; ADD A,L
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Z80_instr_86: ; ADD A,(HL)
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Z80_instr_87: ; ADD A,A
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Z80_instr_88: ; ADC A,B
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Z80_instr_89: ; ADC A,C
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Z80_instr_8A: ; ADC A,D
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Z80_instr_8B: ; ADC A,E
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Z80_instr_8C: ; ADC A,H
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Z80_instr_8D: ; ADC A,L
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Z80_instr_8E: ; ADC A,(HL)
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Z80_instr_8F: ; ADC A,A
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Z80_instr_90: ; SUB B
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Z80_instr_91: ; SUB C
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Z80_instr_92: ; SUB D
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Z80_instr_93: ; SUB E
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Z80_instr_94: ; SUB H
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Z80_instr_95: ; SUB L
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Z80_instr_96: ; SUB (HL)
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Z80_instr_97: ; SUB A
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Z80_instr_98: ; SBC B
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Z80_instr_99: ; SBC C
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Z80_instr_9A: ; SBC D
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Z80_instr_9B: ; SBC E
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Z80_instr_9C: ; SBC H
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Z80_instr_9D: ; SBC L
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Z80_instr_9E: ; SBC (HL)
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Z80_instr_9F: ; SBC A
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Z80_instr_B8: ; CP B
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Z80_instr_B9: ; CP C
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Z80_instr_BA: ; CP D
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Z80_instr_BB: ; CP E
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Z80_instr_BC: ; CP H
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Z80_instr_BD: ; CP L
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Z80_instr_BE: ; CP (HL)
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Z80_instr_BF: ; CP A
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Z80_instr_C6: ; ADD A,n
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Z80_instr_CE: ; ADC A,n
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Z80_instr_D6: ; SUB n
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Z80_instr_DE: ; SBC A,n
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Z80_instr_E3: ; EX (SP),HL
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Z80_instr_F9: ; LD SP,HL
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Z80_instr_FE: ; CP n
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Z80_instr_CB_00: ; RLC B
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Z80_instr_CB_01: ; RLC C
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Z80_instr_CB_02: ; RLC D
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Z80_instr_CB_03: ; RLC E
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Z80_instr_CB_04: ; RLC H
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Z80_instr_CB_05: ; RLC L
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Z80_instr_CB_06: ; RLC (HL)
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Z80_instr_CB_07: ; RLC A
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Z80_instr_CB_08: ; RRC B
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Z80_instr_CB_09: ; RRC C
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Z80_instr_CB_0A: ; RRC D
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Z80_instr_CB_0B: ; RRC E
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Z80_instr_CB_0C: ; RRC H
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Z80_instr_CB_0D: ; RRC L
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Z80_instr_CB_0E: ; RRC (HL)
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Z80_instr_CB_0F: ; RRC A
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Z80_instr_CB_10: ; RL B
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Z80_instr_CB_11: ; RL C
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Z80_instr_CB_12: ; RL D
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Z80_instr_CB_13: ; RL E
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Z80_instr_CB_14: ; RL H
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Z80_instr_CB_15: ; RL L
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Z80_instr_CB_16: ; RL (HL)
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Z80_instr_CB_17: ; RL A
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Z80_instr_CB_18: ; RR B
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Z80_instr_CB_19: ; RR C
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Z80_instr_CB_1A: ; RR D
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Z80_instr_CB_1B: ; RR E
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Z80_instr_CB_1C: ; RR H
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Z80_instr_CB_1D: ; RR L
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Z80_instr_CB_1E: ; RR (HL)
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Z80_instr_CB_1F: ; RR A
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Z80_instr_CB_20: ; SLA B
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Z80_instr_CB_21: ; SLA C
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Z80_instr_CB_22: ; SLA D
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Z80_instr_CB_23: ; SLA E
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Z80_instr_CB_24: ; SLA H
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Z80_instr_CB_25: ; SLA L
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Z80_instr_CB_26: ; SLA (HL)
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Z80_instr_CB_27: ; SLA A
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Z80_instr_CB_28: ; SRA B
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Z80_instr_CB_29: ; SRA C
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Z80_instr_CB_2A: ; SRA D
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Z80_instr_CB_2B: ; SRA E
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Z80_instr_CB_2C: ; SRA H
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Z80_instr_CB_2D: ; SRA L
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Z80_instr_CB_2E: ; SRA (HL)
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Z80_instr_CB_2F: ; SRA A
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Z80_instr_CB_38: ; SRL B
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Z80_instr_CB_39: ; SRL C
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Z80_instr_CB_3A: ; SRL D
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Z80_instr_CB_3B: ; SRL E
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Z80_instr_CB_3C: ; SRL H
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Z80_instr_CB_3D: ; SRL L
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Z80_instr_CB_3E: ; SRL (HL)
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Z80_instr_CB_3F: ; SRL A
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Z80_instr_DD_09: ; ADD IX,BC
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Z80_instr_DD_19: ; ADD IX,DE
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Z80_instr_DD_22: ; LD (nn),IX
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Z80_instr_DD_29: ; ADD IX,IX
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Z80_instr_DD_2A: ; LD IX,(nn)
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Z80_instr_DD_39: ; ADD IX,SP
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Z80_instr_DD_86: ; ADD A,(IX+d)
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Z80_instr_DD_8E: ; ADC A,(IX+d)
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Z80_instr_DD_96: ; SUB (IX+d)
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Z80_instr_DD_9E: ; SBC (IX+d)
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Z80_instr_DD_BE: ; CP (IX+d)
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Z80_instr_DD_E3: ; EX (SP),IX
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Z80_instr_DD_F9: ; LD SP,IX
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Z80_instr_ED_42: ; SBC HL,BC
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Z80_instr_ED_43: ; LD (nn),BC
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Z80_instr_ED_4A: ; ADC HL,BC
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Z80_instr_ED_4B: ; LD BC,(nn)
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Z80_instr_ED_52: ; SBC HL,DE
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Z80_instr_ED_53: ; LD (nn),DE
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Z80_instr_ED_5A: ; ADC HL,DE
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Z80_instr_ED_5B: ; LD DE,(nn)
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Z80_instr_ED_62: ; SBC HL,HL
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Z80_instr_ED_67: ; RRD
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Z80_instr_ED_6A: ; ADC HL,HL
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Z80_instr_ED_6F: ; RLD
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Z80_instr_ED_72: ; SBC HL,SP
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Z80_instr_ED_73: ; LD (nn),SP
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Z80_instr_ED_7A: ; ADC HL,SP
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Z80_instr_ED_7B: ; LD SP,(nn)
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Z80_instr_ED_A0: ; LDI
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Z80_instr_ED_A1: ; CPI
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Z80_instr_ED_A2: ; INI
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Z80_instr_ED_A3: ; OUTI
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Z80_instr_ED_A8: ; LDD
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Z80_instr_ED_A9: ; CPD
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Z80_instr_ED_AA: ; IND
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Z80_instr_ED_AB: ; OUTD
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Z80_instr_ED_B0: ; LDIR
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Z80_instr_ED_B1: ; CPIR
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Z80_instr_ED_B2: ; INIR
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Z80_instr_ED_B3: ; OTIR
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Z80_instr_ED_B8: ; LDDR
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Z80_instr_ED_B9: ; CPDR
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Z80_instr_ED_BA: ; INDR
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Z80_instr_ED_BB: ; OTDR
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Z80_instr_FD_09: ; ADD IY,BC
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Z80_instr_FD_19: ; ADD IY,DE
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Z80_instr_FD_22: ; LD (nn),IY
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Z80_instr_FD_29: ; ADD IY,IY
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Z80_instr_FD_2A: ; LD IY,(nn)
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Z80_instr_FD_39: ; ADD IY,SP
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Z80_instr_FD_86: ; ADD A,(IY+d)
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Z80_instr_FD_8E: ; ADC A,(IY+d)
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Z80_instr_FD_96: ; SUB (IY+d)
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Z80_instr_FD_9E: ; SBC (IY+d)
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Z80_instr_FD_BE: ; CP (IY+d)
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Z80_instr_FD_E3: ; EX (SP),IY
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Z80_instr_FD_F9: ; LD SP,IY
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Z80_instr_xDCB_06: ; RLC (IXY+d)
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Z80_instr_xDCB_0E: ; RRC (IXY+d)
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Z80_instr_xDCB_16: ; RL (IXY+d)
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Z80_instr_xDCB_1E: ; RR (IXY+d)
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Z80_instr_xDCB_26: ; SLA (IXY+d)
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Z80_instr_xDCB_2E: ; SRA (IXY+d)
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Z80_instr_xDCB_3E: ; SRL (IXY+d)
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Z80_illeg_CB_30: ; SLL B
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Z80_illeg_CB_31: ; SLL C
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Z80_illeg_CB_32: ; SLL D
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Z80_illeg_CB_33: ; SLL E
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Z80_illeg_CB_34: ; SLL H
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Z80_illeg_CB_35: ; SLL L
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Z80_illeg_CB_36: ; SLL (HL)
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Z80_illeg_CB_37: ; SLL A
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Z80_illeg_ED_70: ; IN F,(C)
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Z80_illeg_ED_71: ; OUT (C),0
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Z80_illeg_ED_63: ; LD (nn),HL
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Z80_illeg_ED_6B: ; LD HL,(nn)
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Z80_illeg_DD_84: ; ADD A,IXH
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Z80_illeg_DD_85: ; ADD A,IXL
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Z80_illeg_DD_8C: ; ADC A,IXH
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Z80_illeg_DD_8D: ; ADC A,IXL
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Z80_illeg_DD_94: ; SUB A,IXH
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Z80_illeg_DD_95: ; SUB A,IXL
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Z80_illeg_DD_9C: ; SBC A,IXH
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Z80_illeg_DD_9D: ; SBC A,IXL
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Z80_illeg_DD_BC: ; CP IXH
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Z80_illeg_DD_BD: ; CP IXL
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Z80_illeg_FD_84: ; ADD A,IYH
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Z80_illeg_FD_85: ; ADD A,IYL
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Z80_illeg_FD_8C: ; ADC A,IYH
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Z80_illeg_FD_8D: ; ADC A,IYL
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Z80_illeg_FD_94: ; SUB A,IYH
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Z80_illeg_FD_95: ; SUB A,IYL
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Z80_illeg_FD_9C: ; SBC A,IYH
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Z80_illeg_FD_9D: ; SBC A,IYL
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Z80_illeg_FD_BC: ; CP IYH
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Z80_illeg_FD_BD: ; CP IYL
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Z80_illeg_xDCB_00: ; RLC (IXY+d),B
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Z80_illeg_xDCB_01: ; RLC (IXY+d),C
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Z80_illeg_xDCB_02: ; RLC (IXY+d),D
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Z80_illeg_xDCB_03: ; RLC (IXY+d),E
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Z80_illeg_xDCB_04: ; RLC (IXY+d),H
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Z80_illeg_xDCB_05: ; RLC (IXY+d),L
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Z80_illeg_xDCB_07: ; RLC (IXY+d),A
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Z80_illeg_xDCB_08: ; RRC (IXY+d),B
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Z80_illeg_xDCB_09: ; RRC (IXY+d),C
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Z80_illeg_xDCB_0A: ; RRC (IXY+d),D
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Z80_illeg_xDCB_0B: ; RRC (IXY+d),E
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Z80_illeg_xDCB_0C: ; RRC (IXY+d),H
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Z80_illeg_xDCB_0D: ; RRC (IXY+d),L
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Z80_illeg_xDCB_0F: ; RRC (IXY+d),A
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Z80_illeg_xDCB_10: ; RL (IXY+d),B
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Z80_illeg_xDCB_11: ; RL (IXY+d),C
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Z80_illeg_xDCB_12: ; RL (IXY+d),D
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Z80_illeg_xDCB_13: ; RL (IXY+d),E
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Z80_illeg_xDCB_14: ; RL (IXY+d),H
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Z80_illeg_xDCB_15: ; RL (IXY+d),L
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Z80_illeg_xDCB_17: ; RL (IXY+d),A
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Z80_illeg_xDCB_18: ; RR (IXY+d),B
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Z80_illeg_xDCB_19: ; RR (IXY+d),C
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Z80_illeg_xDCB_1A: ; RR (IXY+d),D
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Z80_illeg_xDCB_1B: ; RR (IXY+d),E
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Z80_illeg_xDCB_1C: ; RR (IXY+d),H
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Z80_illeg_xDCB_1D: ; RR (IXY+d),L
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Z80_illeg_xDCB_1F: ; RR (IXY+d),A
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Z80_illeg_xDCB_20: ; SLA (IXY+d),B
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Z80_illeg_xDCB_21: ; SLA (IXY+d),C
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Z80_illeg_xDCB_22: ; SLA (IXY+d),D
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Z80_illeg_xDCB_23: ; SLA (IXY+d),E
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Z80_illeg_xDCB_24: ; SLA (IXY+d),H
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Z80_illeg_xDCB_25: ; SLA (IXY+d),L
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Z80_illeg_xDCB_27: ; SLA (IXY+d),A
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Z80_illeg_xDCB_28: ; SRA (IXY+d),B
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Z80_illeg_xDCB_29: ; SRA (IXY+d),C
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Z80_illeg_xDCB_2A: ; SRA (IXY+d),D
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Z80_illeg_xDCB_2B: ; SRA (IXY+d),E
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Z80_illeg_xDCB_2C: ; SRA (IXY+d),H
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Z80_illeg_xDCB_2D: ; SRA (IXY+d),L
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Z80_illeg_xDCB_2F: ; SRA (IXY+d),A
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Z80_illeg_xDCB_30: ; SLL (IXY+d),B
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Z80_illeg_xDCB_31: ; SLL (IXY+d),C
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Z80_illeg_xDCB_32: ; SLL (IXY+d),D
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Z80_illeg_xDCB_33: ; SLL (IXY+d),E
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Z80_illeg_xDCB_34: ; SLL (IXY+d),H
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Z80_illeg_xDCB_35: ; SLL (IXY+d),L
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Z80_illeg_xDCB_36: ; SLL (IXY+d)
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Z80_illeg_xDCB_37: ; SLL (IXY+d),A
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Z80_illeg_xDCB_38: ; SLR (IXY+d),B
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Z80_illeg_xDCB_39: ; SLR (IXY+d),C
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Z80_illeg_xDCB_3A: ; SLR (IXY+d),D
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Z80_illeg_xDCB_3B: ; SLR (IXY+d),E
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Z80_illeg_xDCB_3C: ; SLR (IXY+d),H
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Z80_illeg_xDCB_3D: ; SLR (IXY+d),L
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Z80_illeg_xDCB_3F: ; SLR (IXY+d),A
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Z80_illeg_xDCB_80: ; RES 0,(IXY+d),B
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Z80_illeg_xDCB_81: ; RES 0,(IXY+d),C
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Z80_illeg_xDCB_82: ; RES 0,(IXY+d),D
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Z80_illeg_xDCB_83: ; RES 0,(IXY+d),E
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Z80_illeg_xDCB_84: ; RES 0,(IXY+d),H
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Z80_illeg_xDCB_85: ; RES 0,(IXY+d),L
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Z80_illeg_xDCB_87: ; RES 0,(IXY+d),A
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Z80_illeg_xDCB_88: ; RES 1,(IXY+d),B
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Z80_illeg_xDCB_89: ; RES 1,(IXY+d),C
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Z80_illeg_xDCB_8A: ; RES 1,(IXY+d),D
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Z80_illeg_xDCB_8B: ; RES 1,(IXY+d),E
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Z80_illeg_xDCB_8C: ; RES 1,(IXY+d),H
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Z80_illeg_xDCB_8D: ; RES 1,(IXY+d),L
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Z80_illeg_xDCB_8F: ; RES 1,(IXY+d),A
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Z80_illeg_xDCB_90: ; RES 2,(IXY+d),B
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Z80_illeg_xDCB_91: ; RES 2,(IXY+d),C
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Z80_illeg_xDCB_92: ; RES 2,(IXY+d),D
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Z80_illeg_xDCB_93: ; RES 2,(IXY+d),E
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Z80_illeg_xDCB_94: ; RES 2,(IXY+d),H
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Z80_illeg_xDCB_95: ; RES 2,(IXY+d),L
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Z80_illeg_xDCB_97: ; RES 2,(IXY+d),A
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Z80_illeg_xDCB_98: ; RES 3,(IXY+d),B
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Z80_illeg_xDCB_99: ; RES 3,(IXY+d),C
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Z80_illeg_xDCB_9A: ; RES 3,(IXY+d),D
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Z80_illeg_xDCB_9B: ; RES 3,(IXY+d),E
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Z80_illeg_xDCB_9C: ; RES 3,(IXY+d),H
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Z80_illeg_xDCB_9D: ; RES 3,(IXY+d),L
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Z80_illeg_xDCB_9F: ; RES 3,(IXY+d),A
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Z80_illeg_xDCB_A0: ; RES 4,(IXY+d),B
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Z80_illeg_xDCB_A1: ; RES 4,(IXY+d),C
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Z80_illeg_xDCB_A2: ; RES 4,(IXY+d),D
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Z80_illeg_xDCB_A3: ; RES 4,(IXY+d),E
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Z80_illeg_xDCB_A4: ; RES 4,(IXY+d),H
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Z80_illeg_xDCB_A5: ; RES 4,(IXY+d),L
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Z80_illeg_xDCB_A7: ; RES 4,(IXY+d),A
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Z80_illeg_xDCB_A8: ; RES 5,(IXY+d),B
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Z80_illeg_xDCB_A9: ; RES 5,(IXY+d),C
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Z80_illeg_xDCB_AA: ; RES 5,(IXY+d),D
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Z80_illeg_xDCB_AB: ; RES 5,(IXY+d),E
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Z80_illeg_xDCB_AC: ; RES 5,(IXY+d),H
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Z80_illeg_xDCB_AD: ; RES 5,(IXY+d),L
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Z80_illeg_xDCB_AF: ; RES 5,(IXY+d),A
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Z80_illeg_xDCB_B0: ; RES 6,(IXY+d),B
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Z80_illeg_xDCB_B1: ; RES 6,(IXY+d),C
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Z80_illeg_xDCB_B2: ; RES 6,(IXY+d),D
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Z80_illeg_xDCB_B3: ; RES 6,(IXY+d),E
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Z80_illeg_xDCB_B4: ; RES 6,(IXY+d),H
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Z80_illeg_xDCB_B5: ; RES 6,(IXY+d),L
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Z80_illeg_xDCB_B7: ; RES 6,(IXY+d),A
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Z80_illeg_xDCB_B8: ; RES 7,(IXY+d),B
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Z80_illeg_xDCB_B9: ; RES 7,(IXY+d),C
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Z80_illeg_xDCB_BA: ; RES 7,(IXY+d),D
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Z80_illeg_xDCB_BB: ; RES 7,(IXY+d),E
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Z80_illeg_xDCB_BC: ; RES 7,(IXY+d),H
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Z80_illeg_xDCB_BD: ; RES 7,(IXY+d),L
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Z80_illeg_xDCB_BF: ; RES 7,(IXY+d),A
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Z80_illeg_xDCB_C0: ; SET 0,(IXY+d),B
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Z80_illeg_xDCB_C1: ; SET 0,(IXY+d),C
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Z80_illeg_xDCB_C2: ; SET 0,(IXY+d),D
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Z80_illeg_xDCB_C3: ; SET 0,(IXY+d),E
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Z80_illeg_xDCB_C4: ; SET 0,(IXY+d),H
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Z80_illeg_xDCB_C5: ; SET 0,(IXY+d),L
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Z80_illeg_xDCB_C7: ; SET 0,(IXY+d),A
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Z80_illeg_xDCB_C8: ; SET 1,(IXY+d),B
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Z80_illeg_xDCB_C9: ; SET 1,(IXY+d),C
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Z80_illeg_xDCB_CA: ; SET 1,(IXY+d),D
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Z80_illeg_xDCB_CB: ; SET 1,(IXY+d),E
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Z80_illeg_xDCB_CC: ; SET 1,(IXY+d),H
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Z80_illeg_xDCB_CD: ; SET 1,(IXY+d),L
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Z80_illeg_xDCB_CF: ; SET 1,(IXY+d),A
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Z80_illeg_xDCB_D0: ; SET 2,(IXY+d),B
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Z80_illeg_xDCB_D1: ; SET 2,(IXY+d),C
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Z80_illeg_xDCB_D2: ; SET 2,(IXY+d),D
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Z80_illeg_xDCB_D3: ; SET 2,(IXY+d),E
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Z80_illeg_xDCB_D4: ; SET 2,(IXY+d),H
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Z80_illeg_xDCB_D5: ; SET 2,(IXY+d),L
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Z80_illeg_xDCB_D7: ; SET 2,(IXY+d),A
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Z80_illeg_xDCB_D8: ; SET 3,(IXY+d),B
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Z80_illeg_xDCB_D9: ; SET 3,(IXY+d),C
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Z80_illeg_xDCB_DA: ; SET 3,(IXY+d),D
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Z80_illeg_xDCB_DB: ; SET 3,(IXY+d),E
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Z80_illeg_xDCB_DC: ; SET 3,(IXY+d),H
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Z80_illeg_xDCB_DD: ; SET 3,(IXY+d),L
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Z80_illeg_xDCB_DF: ; SET 3,(IXY+d),A
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Z80_illeg_xDCB_E0: ; SET 4,(IXY+d),B
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Z80_illeg_xDCB_E1: ; SET 4,(IXY+d),C
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Z80_illeg_xDCB_E2: ; SET 4,(IXY+d),D
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Z80_illeg_xDCB_E3: ; SET 4,(IXY+d),E
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Z80_illeg_xDCB_E4: ; SET 4,(IXY+d),H
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Z80_illeg_xDCB_E5: ; SET 4,(IXY+d),L
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Z80_illeg_xDCB_E7: ; SET 4,(IXY+d),A
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Z80_illeg_xDCB_E8: ; SET 5,(IXY+d),B
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Z80_illeg_xDCB_E9: ; SET 5,(IXY+d),C
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Z80_illeg_xDCB_EA: ; SET 5,(IXY+d),D
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Z80_illeg_xDCB_EB: ; SET 5,(IXY+d),E
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Z80_illeg_xDCB_EC: ; SET 5,(IXY+d),H
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Z80_illeg_xDCB_ED: ; SET 5,(IXY+d),L
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Z80_illeg_xDCB_EF: ; SET 5,(IXY+d),A
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Z80_illeg_xDCB_F0: ; SET 6,(IXY+d),B
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Z80_illeg_xDCB_F1: ; SET 6,(IXY+d),C
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Z80_illeg_xDCB_F2: ; SET 6,(IXY+d),D
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Z80_illeg_xDCB_F3: ; SET 6,(IXY+d),E
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Z80_illeg_xDCB_F4: ; SET 6,(IXY+d),H
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Z80_illeg_xDCB_F5: ; SET 6,(IXY+d),L
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Z80_illeg_xDCB_F7: ; SET 6,(IXY+d),A
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Z80_illeg_xDCB_F8: ; SET 7,(IXY+d),B
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Z80_illeg_xDCB_F9: ; SET 7,(IXY+d),C
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Z80_illeg_xDCB_FA: ; SET 7,(IXY+d),D
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Z80_illeg_xDCB_FB: ; SET 7,(IXY+d),E
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Z80_illeg_xDCB_FC: ; SET 7,(IXY+d),H
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Z80_illeg_xDCB_FD: ; SET 7,(IXY+d),L
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Z80_illeg_xDCB_FF: ; SET 7,(IXY+d),A
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jmp ZVM_next ; XXX provide implementation
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