175 lines
3.3 KiB
ArmAsm
175 lines
3.3 KiB
ArmAsm
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//
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// JiffyDOS protocol support for IEC - optimized load loop
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//
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#if CONFIG_IEC_JIFFYDOS && !CONFIG_MEMORY_MODEL_60K
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// Note: original JiffyDOS LOAD loop checks for RUN/STOP key every time a sector is read,
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// see description at https://sites.google.com/site/h2obsession/CBM/C128/JiffySoft128
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//
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// For simplicity and some space savings, our routine does not check the RUN/STOP key at all;
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// the protocol is fast enough (especially with modern flash mediums) that probably nobody
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// will want to terminate the loading.
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load_jiffydos:
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// Timing is critical, do not allow interrupts
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sei
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#if CONFIG_IEC_BLANK_SCREEN
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// Preserve register with screen status (blank/visibe)
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lda VIC_SCROLY
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sta TBTCNT
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// Blank screen to make sure no sprite/badline will interrupt
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jsr screen_off
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// Preserve 3 lowest bits of CIA2_PRA XXX deduplicate this
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lda CIA2_PRA
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and #%00000111
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sta C3PO
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#else
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// Store previous sprite status in temporary variable
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jsr jiffydos_prepare
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sta TBTCNT
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#endif
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// A trick to shorten EAL update time
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ldy #$FF
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// FALLTROUGH
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load_jiffydos_loop:
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// Wait until device is ready to send (releases CLK)
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jsr iec_wait_for_clk_release
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// Prepare 'start sending' message
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lda CIA2_PRA
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and #$FF - BIT_CIA2_PRA_DAT_OUT // release
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#if CONFIG_IEC_BLANK_SCREEN
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// It seems JiffyDOS needs some time here; waste few cycles
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nop
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jsr iec_wait_rts
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// Ask device to start sending bits
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sta CIA2_PRA
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#else
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// Wait for appropriate moment, ask device to start sending bits
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tax
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jsr jiffydos_wait_line
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stx CIA2_PRA // cycles: 4
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#endif
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// Prepare 'data pull' byte, cycles: 3 + 2 + 2 = 7
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lda C3PO
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ora #BIT_CIA2_PRA_DAT_OUT // pull
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tax
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// Delay, JiffyDOS needs some time, 4 cycles
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nop
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nop
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// Get bits, cycles: 4 + 2 + 2 = 8
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lda CIA2_PRA // bits 0 and 1 on CLK/DATA
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lsr
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lsr
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// Delay, JiffyDOS needs some time, 2 cycles
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nop
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// Get bits, cycles: 4 + 2 + 2 = 8
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ora CIA2_PRA // bits 2 and 3 on CLK/DATA
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lsr
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lsr
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// Get bits, cycles: 3 + 4 + 2 + 2 = 11
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eor C3PO
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eor CIA2_PRA // bits 4 and 5 on CLK/DATA
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lsr
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lsr
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// Get bits, cycles: 3 + 4 = 7
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eor C3PO
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eor CIA2_PRA // bits 6 and 7 on CLK/DATA
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// Store retrieved byte, cycles: 2 + 6 = 8
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iny // NTSC needs this delay
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sta (EAL),y // not compatible with CONFIG_MEMORY_MODEL_60K
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// Retrieve status bits, cycles: 4
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bit CIA2_PRA
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// Pull DATA at the end, cycles: 4
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stx CIA2_PRA
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// If CLK line not active - this was the last byte
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bvs load_jiffydos_end
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// Handle EAL
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cpy #$FF
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bne load_jiffydos_loop
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inc EAL+1
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jmp load_jiffydos_loop
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load_jiffydos_end:
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// Save last byte
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tax
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// Update EAL
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tya
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sec
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adc EAL+0
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sta EAL+0
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bcc !+
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inc EAL+1
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!:
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// Indicate that no byte waits in output buffer
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lda #$00
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sta C3PO
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// Restore proper IECPROTO value
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lda #$01
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sta IECPROTO
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#if CONFIG_IEC_BLANK_SCREEN
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// Restore screen state
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lda TBTCNT
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sta VIC_SCROLY
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#else
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// Re-enable sprites
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lda TBTCNT
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sta VIC_SPENA
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#endif
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// Store last byte as unoptimized LOAD routine would
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stx TBTCNT
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// No need to re-enable interrupts; other IEC routines
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// called by LOAD will do this nevertheless
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// End of load loop
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jmp load_iec_loop_end
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#endif // CONFIG_IEC_JIFFYDOS and not CONFIG_MEMORY_MODEL_60K
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