144 lines
1.8 KiB
ArmAsm
144 lines
1.8 KiB
ArmAsm
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; Z80 Virtual Machine banking support
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;
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ZVM_bank0_vectab:
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!word ZVM_bank0_fetch_via_PC_inc
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!word ZVM_bank0_fetch_stack
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!word ZVM_bank0_store_stack
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; XXX add remaining routines here
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ZVM_bank1_vectab:
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!word ZVM_bank1_fetch_via_PC_inc
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!word ZVM_bank1_fetch_stack
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!word ZVM_bank1_store_stack
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; XXX add remaining routines here
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;
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; Bank switching routines
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;
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ZVM_set_bank_0:
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lda #$00
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sta BANK_ID
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; XXX use DMAgic to switch banks (vectors on zeropage)
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rts
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ZVM_set_bank_1:
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lda #$01
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sta BANK_ID
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; XXX use DMAgic to switch banks (vectors on zeropage)
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; Since all the Z80 bank 1 memory is located in $0005:$xxxx,
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; we can set some bytes in certain pointers for faster execution
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lda #$05
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sta PTR_IXY_d+2
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sta PTR_DATA+2
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rts
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;
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; Memory access routines
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;
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ZVM_bank0_fetch_via_PC_inc:
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lda REG_PC+0
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sta PTR_DATA+0
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ldy REG_PC+1
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lda z80_atable_mi_bank0,y
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sta PTR_DATA+1
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lda z80_atable_hi_bank0,y
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sta PTR_DATA+2
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lda [PTR_DATA], z
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inw REG_PC
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rts
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ZVM_bank1_fetch_via_PC_inc:
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lda [REG_PC], z
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inw REG_PC
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rts
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ZVM_bank0_fetch_stack:
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ldx REG_SP+0
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stx PTR_DATA+0
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ldy REG_SP+1
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ldx z80_atable_mi_bank0,y
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stx PTR_DATA+1
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ldx z80_atable_hi_bank0,y
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stx PTR_DATA+2
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lda [PTR_DATA], z
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inw REG_SP
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rts
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ZVM_bank1_fetch_stack:
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lda [REG_SP], z
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inw REG_SP
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rts
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ZVM_bank0_store_stack:
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dew REG_SP
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ldx REG_SP+0
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stx PTR_DATA+0
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ldy REG_SP+1
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ldx z80_atable_mi_bank0,y
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stx PTR_DATA+1
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ldx z80_atable_hi_bank0,y
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stx PTR_DATA+2
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sta [PTR_DATA], z
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rts
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ZVM_bank1_store_stack:
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dew REG_SP
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sta [REG_SP], z
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rts
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; XXX cleanup code below
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ZVM_fetch_IO:
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; XXX fetch addresses via ADDR_IO - but which ones are safe? Should we have a whitelist?
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lda #$00
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sta REG_A
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rts
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ZVM_store_IO:
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; XXX again, we should have a whitelist of addresses
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rts
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