114 lines
2.5 KiB
ArmAsm
114 lines
2.5 KiB
ArmAsm
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;;
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;; Official Kernal routine, described in:
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;;
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;; - [RG64] C64 Programmer's Reference Guide - page 285
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;; - [CM64] Compute's Mapping the Commodore 64 - page 238
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;;
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;; CPU registers that has to be preserved (see [RG64]): none
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;;
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ioinit:
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; Set $00/$01 port mode and value
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; We want BASIC and KERNAL ROMs mapped, and datasette motor off
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; (https://www.c64-wiki.com/wiki/Zeropage)
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;; XXX - Work around VICE bug: Writing $00 before $01 results in rubbish in $01
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;; after. https://sourceforge.net/p/vice-emu/bugs/1057/
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lda #$27
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ldx #$2F
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sta CPU_R6510
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stx CPU_D6510
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;; Silence the SID chips
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ldy #$00
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*
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lda SID_SIGVOL, Y
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and #$F0
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sta SID_SIGVOL, Y
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tya
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clc
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adc #$20
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tay
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cpy #$80 ; $20 * amount of chips to silence, $80 to silence 4 chips
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bne -
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;; Detect video system (PAL/NTSC), use Graham's method, as it's short and reliable
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;; see here: https://codebase64.org/doku.php?id=base:detect_pal_ntsc
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ioinit_w0:
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lda VIC_RASTER
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ioinit_w1:
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cmp VIC_RASTER
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beq ioinit_w1
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bmi ioinit_w0
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;; Result in A, if no interrupt happened during the test:
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;; #$37 -> 312 rasterlines, PAL, VIC 6569
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;; #$06 -> 263 rasterlines, NTSC, VIC 6567R8
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;; #$05 -> 262 rasterlines, NTSC, VIC 6567R56A
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cmp #$07
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bcs ioinit_pal
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ioinit_ntsc:
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lda #$00
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beq +
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ioinit_pal:
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lda #$01
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*
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sta PALNTSC
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;; XXX: calibrate TOD for both CIA's, see here: https://codebase64.org/doku.php?id=base:efficient_tod_initialisation
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;; Enable CIA1 IRQ and ~50Hz timer (https://csdb.dk/forums/?roomid=11&topicid=69037)
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lda #$7F
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sta CIA1_ICR ; disable all
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;; Set timer interval to ~1/60th of a second
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;; (This value was calculated by running a custom IRQ handler on a C64
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;; with original KERNAL, and writing the values of $DC04/5 to the screen
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;; in the IRQ handler to see roughly what value the timers must be set to)
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;; ldy #<16380
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;; ldx #>16380
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;; PAL C64 (https://codebase64.org/doku.php?id=base:cpu_clocking),
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;; is clocked at 0.985248 MHz, so that 1/60s is 16421 CPU cycles
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ldy #<16421
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ldx #>16421
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lda PALNTSC
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bne +
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;; NTSC C64 (https://codebase64.org/doku.php?id=base:cpu_clocking),
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;; is clocked at 1.022727 MHz, so that 1/60s is 17045 CPU cycles
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ldy #<17045
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ldx #>17045
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;; Store the IRQ timing constant to CIA chip
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*
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sty CIA1_TIMALO
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stx CIA1_TIMAHI
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;; Enable timer interrupt
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lda #$81
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sta CIA1_ICR
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;; Enable timer A to run continuously (http://codebase64.org/doku.php?id=base:timerinterrupts)
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lda #$11
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sta CIA1_CRA
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lda CIA1_ICR
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;; Set DDR on CIA2 for IEC bus, VIC-II banking
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lda #$3B
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sta CIA2_DDRA
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;; Set IEC bus to its initial idle state
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jmp iec_set_idle
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