95 lines
3.8 KiB
ArmAsm
95 lines
3.8 KiB
ArmAsm
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;
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; Z80 data load instructions, 16 bit
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;
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!macro Z80_LD_REGnn_nn .REGnn {
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+Z80_FETCH_VIA_PC_INC
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sta .REGnn+0
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+Z80_FETCH_VIA_PC_INC
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sta .REGnn+1
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jmp ZVM_next
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}
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Z80_instr_01: +Z80_LD_REGnn_nn REG_BC ; LD BC,nn
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Z80_instr_11: +Z80_LD_REGnn_nn REG_DE ; LD DE,nn
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Z80_instr_21: +Z80_LD_REGnn_nn REG_HL ; LD HL,nn
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Z80_instr_31: +Z80_LD_REGnn_nn REG_SP ; LD SP,nn
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Z80_instr_DD_21: +Z80_LD_REGnn_nn REG_IX ; LD IX,nn
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Z80_instr_FD_21: +Z80_LD_REGnn_nn REG_IY ; LD IY,nn
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!macro Z80_LD_REGnn_REGnn .REGnn1, .REGnn2 {
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lda .REGnn2+0
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sta .REGnn1+0
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jsr .REGnn2+1
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sta .REGnn1+1
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jmp ZVM_next
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}
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Z80_instr_F9: +Z80_LD_REGnn_REGnn REG_SP, REG_HL ; LD SP,HL
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Z80_instr_DD_F9: +Z80_LD_REGnn_REGnn REG_SP, REG_IX ; LD SP,IX
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Z80_instr_FD_F9: +Z80_LD_REGnn_REGnn REG_SP, REG_IY ; LD SP,IY
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!macro Z80_LD_VIA_nn_REGnn .REGnn {
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ldx .REGnn+0
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+Z80_STORE_VIA_nn
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lda .REGnn+1
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+Z80_STORE_VIA_plus1
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jmp ZVM_next
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}
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Z80_illeg_ED_63: ; LD (nn),HL
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Z80_instr_22: +Z80_LD_VIA_nn_REGnn REG_HL ; LD (nn),HL
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Z80_instr_ED_43: +Z80_LD_VIA_nn_REGnn REG_BC ; LD (nn),BC
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Z80_instr_ED_53: +Z80_LD_VIA_nn_REGnn REG_DE ; LD (nn),DE
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Z80_instr_DD_22: +Z80_LD_VIA_nn_REGnn REG_IX ; LD (nn),IX
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Z80_instr_FD_22: +Z80_LD_VIA_nn_REGnn REG_IY ; LD (nn),IY
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Z80_instr_ED_73: +Z80_LD_VIA_nn_REGnn REG_SP ; LD (nn),SP
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!macro Z80_LD_REGnn_VIA_nn .REGnn {
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+Z80_FETCH_VIA_nn
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sta .REGnn+0
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+Z80_FETCH_VIA_plus1
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sta .REGnn+1
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jmp ZVM_next
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}
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Z80_illeg_ED_6B: ; LD HL,(nn)
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Z80_instr_2A: +Z80_LD_REGnn_VIA_nn REG_HL ; LD HL,(nn)
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Z80_instr_ED_4B: +Z80_LD_REGnn_VIA_nn REG_BC ; LD BC,(nn)
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Z80_instr_ED_5B: +Z80_LD_REGnn_VIA_nn REG_DE ; LD DE,(nn)
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Z80_instr_DD_2A: +Z80_LD_REGnn_VIA_nn REG_IX ; LD IX,(nn)
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Z80_instr_FD_2A: +Z80_LD_REGnn_VIA_nn REG_IY ; LD IY,(nn)
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Z80_instr_ED_7B: +Z80_LD_REGnn_VIA_nn REG_SP ; LD SP,(nn)
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!macro Z80_PUSH_REGnn .REGnn {
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lda .REGnn+1
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+Z80_STORE_STACK
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lda .REGnn+0
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+Z80_STORE_STACK
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jmp ZVM_next
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}
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Z80_instr_C5: +Z80_PUSH_REGnn REG_BC ; PUSH BC
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Z80_instr_D5: +Z80_PUSH_REGnn REG_DE ; PUSH DE
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Z80_instr_E5: +Z80_PUSH_REGnn REG_HL ; PUSH HL
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Z80_instr_F5: +Z80_PUSH_REGnn REG_AF ; PUSH AF
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Z80_instr_DD_E5: +Z80_PUSH_REGnn REG_IX ; PUSH IX
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Z80_instr_FD_E5: +Z80_PUSH_REGnn REG_IY ; PUSH IY
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!macro Z80_POP_REGnn .REGnn {
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+Z80_FETCH_STACK
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sta .REGnn+0
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+Z80_FETCH_STACK
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lda .REGnn+1
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jmp ZVM_next
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}
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Z80_instr_C1: +Z80_POP_REGnn REG_BC ; POP BC
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Z80_instr_D1: +Z80_POP_REGnn REG_DE ; POP DE
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Z80_instr_E1: +Z80_POP_REGnn REG_HL ; POP HL
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Z80_instr_F1: +Z80_POP_REGnn REG_AF ; POP AF
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Z80_instr_DD_E1: +Z80_POP_REGnn REG_IX ; POP IX
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Z80_instr_FD_E1: +Z80_POP_REGnn REG_IY ; POP IY
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