84 lines
2.1 KiB
ArmAsm
84 lines
2.1 KiB
ArmAsm
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;
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; Z80 instruction implementation - SRL
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;
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!macro Z80_SRL_REGn .REGn {
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clc
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ror .REGn
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ldx .REGn
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bra Z80_common_SRL
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}
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!macro Z80_SRL_VIA_HL {
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+Z80_FETCH_VIA_HL
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clc
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ror
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+Z80_STORE_BACK_VIA_HL
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bra Z80_common_SRL_VIA
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}
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!macro Z80_SRL_VIA_IXY_d {
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lda [PTR_IXY_d] ,z
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clc
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ror
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; FALLTROUGH
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}
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!macro Z80_SRL_VIA_IXY_d_REGn .REGn {
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lda [PTR_IXY_d] ,z
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clc
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ror
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sta .REGn
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bra Z80_common_SRL_VIA_IXY_d
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}
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Z80_instr_CB_38: +Z80_SRL_REGn REG_B ; SRL B
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Z80_instr_CB_39: +Z80_SRL_REGn REG_C ; SRL C
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Z80_instr_CB_3A: +Z80_SRL_REGn REG_D ; SRL D
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Z80_instr_CB_3B: +Z80_SRL_REGn REG_E ; SRL E
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Z80_instr_CB_3C: +Z80_SRL_REGn REG_H ; SRL H
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Z80_instr_CB_3D: +Z80_SRL_REGn REG_L ; SRL L
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Z80_instr_CB_3F: +Z80_SRL_REGn REG_A ; SRL A
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Z80_instr_CB_3E: +Z80_SRL_VIA_HL ; SRL (HL)
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Z80_instr_xDCB_3E: +Z80_SRL_VIA_IXY_d ; SRL (IXY+d)
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; FALLTROUGH
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Z80_common_SRL_VIA_IXY_d:
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sta [PTR_IXY_d],z
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; FALLTROUGH
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Z80_common_SRL_VIA:
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tax
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; FALLTROUGH
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Z80_common_SRL:
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lda z80_ftable_IN_OR_XOR, x
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sta REG_F
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+bcc ZVM_next
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+Z80_PUT_1_CF
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jmp ZVM_next
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Z80_illeg_xDCB_38: +Z80_SRL_VIA_IXY_d_REGn REG_B ; SLR (IXY+d),B
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Z80_illeg_xDCB_39: +Z80_SRL_VIA_IXY_d_REGn REG_C ; SLR (IXY+d),C
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Z80_illeg_xDCB_3A: +Z80_SRL_VIA_IXY_d_REGn REG_D ; SLR (IXY+d),D
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Z80_illeg_xDCB_3B: +Z80_SRL_VIA_IXY_d_REGn REG_E ; SLR (IXY+d),E
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Z80_illeg_xDCB_3C: +Z80_SRL_VIA_IXY_d_REGn REG_H ; SLR (IXY+d),H
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Z80_illeg_xDCB_3D: +Z80_SRL_VIA_IXY_d_REGn REG_L ; SLR (IXY+d),L
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Z80_illeg_xDCB_3F: +Z80_SRL_VIA_IXY_d_REGn REG_A ; SLR (IXY+d),A
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