107 lines
2.3 KiB
ArmAsm
107 lines
2.3 KiB
ArmAsm
// #LAYOUT# STD * #TAKE
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// #LAYOUT# * KERNAL_0 #TAKE
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// #LAYOUT# * * #IGNORE
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//
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// JiffyDOS protocol support for IEC - byte transfer
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//
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#if CONFIG_IEC_JIFFYDOS
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jiffydos_tx_byte:
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// Timing is critical, do not allow interrupts
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sei
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// If EOI requested (carry flag set), mark this in IECPROTO as 0
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bcc !+
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dec IECPROTO // turns 1 into 0
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!:
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// Store .X and .Y on the stack - preserve them
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phx_trash_a
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phy_trash_a
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// Make sure we are not sending data on ATN
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jsr iec_release_atn
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// Store previous sprite status on stack
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jsr jiffydos_prepare
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pha
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// Prepare nibbles to send
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lda TBTCNT
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and #$0F
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tax
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lda jiffydos_bittable, X // low nibble has to be encoded
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pha
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lda TBTCNT
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and #$F0
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pha
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// Prepare value for device notification
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ldx C3PO
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// Wait till receiver is ready
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jsr iec_wait_for_data_release
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// Wait till it is safe to send data
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jsr jiffydos_wait_line
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// Notify device that we are going to send byte by releasing everything
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stx CIA2_PRA // cycles: 4
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// Send high nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 3 + 4 = 24
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pla // retrieve high nibble from stack
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ora C3PO // restore VIC-II and RS-232 bits
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sta CIA2_PRA // bits 4 and 5 on CLK/DATA
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lsr // move bits 6 and 7 to positions 4 and 5
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lsr
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and #%00110000 // clear everything but CLK/DATA
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ora C3PO
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sta CIA2_PRA // bits 6 and 7 on CLK/DATA
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// Send low nibble; cycles: 4 + 3 + 4 + 2 + 2 + 2 + 4 = 21
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pla // retrieve low nibble from stack
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ora C3PO // restore VIC-II and RS-232 bits
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sta CIA2_PRA
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lsr
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lsr
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and #%00110000 // clear everything but CLK/DATA
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sta CIA2_PRA
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// Signal EOI if needed; cycles till no EOI: 3 + 3 + 2 + 2 + 4 = 14
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lda C3PO
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ldx IECPROTO
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beq jiffydos_tx_byte_wait_eoi
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// FALLTROUGH
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jiffydos_tx_byte_finalize:
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ora #BIT_CIA2_PRA_CLK_OUT // pull CLK
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sta CIA2_PRA
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// Restore proper IECPROTO value
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lda #$01
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sta IECPROTO
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// Re-enable sprites and interrupts
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pla
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sta VIC_SPENA
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cli
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// Return success
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jmp iec_return_success
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jiffydos_tx_byte_wait_eoi:
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sta CIA2_PRA
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jsr iec_wait20us
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lda C3PO
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jmp jiffydos_tx_byte_finalize
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#endif // CONFIG_IEC_JIFFYDOS
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