421 lines
11 KiB
ArmAsm
421 lines
11 KiB
ArmAsm
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;
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; Z80 Virtual Machine core routines
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;
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ZVM_entry:
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jsr ZVM_init
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; XXX fetch BDOS and Command Processor
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jmp ZVM_next
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ZVM_init:
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; Reset registers and internal data
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ldz #$00 ; .Z is required to be 0 all the time
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lda #$00
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tay
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@1:
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sta REG_AF, y
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iny
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cmp #(REG_IFF2+1)
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bne @1
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; XXX what is the initial SP value?
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; XXX clean memory
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jmp ZVM_set_bank_1
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ZVM_store_next:
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sta [PTR_DATA],z
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; unimplemented/illegal instructions
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Z80_illegal__DD:
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Z80_illegal__ED:
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Z80_illegal__FD:
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Z80_illegal__DDCB:
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Z80_illegal__FDCB:
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; LD instructions with no effect
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Z80_instr_40: ; LD B,B
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Z80_instr_49: ; LD C,C
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Z80_instr_52: ; LD D,D
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Z80_instr_5B: ; LD E,E
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Z80_instr_64: ; LH H,H
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Z80_instr_6D: ; LD L,L
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Z80_instr_7F: ; LD A,A
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; For interrupts (not emulated as of yet)
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Z80_instr_ED_46: ; IM 0
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Z80_instr_ED_56: ; IM 1
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Z80_instr_ED_5E: ; IM 2
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; Real NOP
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Z80_instr_00: ; NOP
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ZVM_next: ; fetch and execute next opcode
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jsr (VEC_fetch_value)
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asl
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tax
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bcs @1
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jmp (Z80_vectab_0) ; execute opcode $00-$7F
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@1: jmp (Z80_vectab_1) ; execute opcode $80-$FF
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Z80_instr_CB: ; #CB
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jsr (VEC_fetch_value)
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asl
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tax
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bcs @1
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jmp (Z80_vectab_CB_0) ; execute opcode $00-$7F
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@1: jmp (Z80_vectab_CB_1) ; execute opcode $80-$FF
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Z80_instr_DD: ; #DD
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jsr (VEC_fetch_value)
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asl
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tax
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bcs @1
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jmp (Z80_vectab_DD_0) ; execute opcode $00-$7F
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@1: jmp (Z80_vectab_DD_1) ; execute opcode $80-$FF
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Z80_instr_ED: ; #ED
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jsr (VEC_fetch_value)
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asl
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tax
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bcs @1
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jmp (Z80_vectab_ED_0) ; execute opcode $00-$7F
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@1: jmp (Z80_vectab_ED_1) ; execute opcode $80-$FF
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Z80_instr_FD: ; #FD
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jsr (VEC_fetch_value)
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asl
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tax
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bcs @1
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jmp (Z80_vectab_FD_0) ; execute opcode $00-$7F
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@1: jmp (Z80_vectab_FD_1) ; execute opcode $80-$FF
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;
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; Not implemented yet - XXX implement them!
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;
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Z80_instr_DD_CB: ; #DDCB
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Z80_instr_FD_CB: ; #FDCB
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Z80_instr_01: ; LD BC,nn
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Z80_instr_02: ; LD (BC),A
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Z80_instr_09: ; ADD HL,BC
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Z80_instr_0A: ; LD A,(BC)
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Z80_instr_11: ; LD DE,nn
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Z80_instr_12: ; LD (DE),A
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Z80_instr_19: ; ADD HL,DE
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Z80_instr_1A: ; LD A,(DE)
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Z80_instr_21: ; LD HL,nn
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Z80_instr_22: ; LD (nn),HL
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Z80_instr_27: ; DAA
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Z80_instr_29: ; ADD HL,HL
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Z80_instr_2A: ; LD HL,(nn)
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Z80_instr_2F: ; CPL
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Z80_instr_31: ; LD SP,nn
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Z80_instr_32: ; LD (nn),A
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Z80_instr_37: ; SCF
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Z80_instr_39: ; ADD HL,SP
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Z80_instr_3A: ; LD A,(nn)
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Z80_instr_3F: ; CCF
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Z80_instr_76: ; HALT
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Z80_instr_80: ; ADD A,B
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Z80_instr_81: ; ADD A,C
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Z80_instr_82: ; ADD A,D
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Z80_instr_83: ; ADD A,E
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Z80_instr_84: ; ADD A,H
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Z80_instr_85: ; ADD A,L
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Z80_instr_86: ; ADD A,(HL)
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Z80_instr_87: ; ADD A,A
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Z80_instr_88: ; ADC A,B
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Z80_instr_89: ; ADC A,C
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Z80_instr_8A: ; ADC A,D
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Z80_instr_8B: ; ADC A,E
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Z80_instr_8C: ; ADC A,H
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Z80_instr_8D: ; ADC A,L
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Z80_instr_8E: ; ADC A,(HL)
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Z80_instr_8F: ; ADC A,A
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Z80_instr_90: ; SUB B
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Z80_instr_91: ; SUB C
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Z80_instr_92: ; SUB D
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Z80_instr_93: ; SUB E
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Z80_instr_94: ; SUB H
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Z80_instr_95: ; SUB L
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Z80_instr_96: ; SUB (HL)
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Z80_instr_97: ; SUB A
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Z80_instr_98: ; SBC B
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Z80_instr_99: ; SBC C
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Z80_instr_9A: ; SBC D
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Z80_instr_9B: ; SBC E
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Z80_instr_9C: ; SBC H
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Z80_instr_9D: ; SBC L
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Z80_instr_9E: ; SBC (HL)
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Z80_instr_9F: ; SBC A
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Z80_instr_A0: ; AND B
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Z80_instr_A1: ; AND C
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Z80_instr_A2: ; AND D
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Z80_instr_A3: ; AND E
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Z80_instr_A4: ; AND H
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Z80_instr_A5: ; AND L
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Z80_instr_A6: ; AND (HL)
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Z80_instr_A7: ; AND A
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Z80_instr_A8: ; XOR B
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Z80_instr_A9: ; XOR C
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Z80_instr_AA: ; XOR D
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Z80_instr_AB: ; XOR E
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Z80_instr_AC: ; XOR H
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Z80_instr_AD: ; XOR L
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Z80_instr_AE: ; XOR (HL)
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Z80_instr_AF: ; XOR A
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Z80_instr_B0: ; OR B
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Z80_instr_B1: ; OR C
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Z80_instr_B2: ; OR D
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Z80_instr_B3: ; OR E
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Z80_instr_B4: ; OR H
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Z80_instr_B5: ; OR L
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Z80_instr_B6: ; OR (HL)
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Z80_instr_B7: ; OR A
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Z80_instr_B8: ; CP B
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Z80_instr_B9: ; CP C
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Z80_instr_BA: ; CP D
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Z80_instr_BB: ; CP E
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Z80_instr_BC: ; CP H
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Z80_instr_BD: ; CP L
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Z80_instr_BE: ; CP (HL)
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Z80_instr_BF: ; CP A
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Z80_instr_C0: ; RET NZ
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Z80_instr_C4: ; CALL NZ,nn
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Z80_instr_C6: ; ADD A,n
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Z80_instr_C7: ; RST 00H
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Z80_instr_C8: ; RET z
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Z80_instr_C9: ; RET
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Z80_instr_CC: ; CALL Z,nn
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Z80_instr_CD: ; CALL nn
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Z80_instr_CE: ; ADC A,n
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Z80_instr_CF: ; RST 08H
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Z80_instr_D0: ; RET NC
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Z80_instr_D3: ; OUT (n), A
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Z80_instr_D4: ; CALL NC,nn
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Z80_instr_D6: ; SUB n
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Z80_instr_D7: ; RST 10H
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Z80_instr_D8: ; RET C
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Z80_instr_DB: ; IN A,(n)
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Z80_instr_DC: ; CALL C,nn
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Z80_instr_DE: ; SBC A,n
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Z80_instr_DF: ; RST 18H
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Z80_instr_E0: ; RET PO
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Z80_instr_E3: ; EX (SP),HL
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Z80_instr_E4: ; CALL PO,nn
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Z80_instr_E6: ; AND n
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Z80_instr_E7: ; RST 20H
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Z80_instr_E8: ; RET PE
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Z80_instr_EC: ; CALL PE,nn
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Z80_instr_EE: ; XOR n
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Z80_instr_EF: ; RST 28H
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Z80_instr_F0: ; RET P
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Z80_instr_F4: ; CALL P,nn
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Z80_instr_F6: ; OR n
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Z80_instr_F7: ; RST 30H
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Z80_instr_F8: ; RET M
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Z80_instr_F9: ; LD SP,HL
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Z80_instr_FC: ; CALL M,nn
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Z80_instr_FE: ; CP n
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Z80_instr_FF: ; RST 38H
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Z80_instr_CB_00: ; RLC B
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Z80_instr_CB_01: ; RLC C
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Z80_instr_CB_02: ; RLC D
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Z80_instr_CB_03: ; RLC E
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Z80_instr_CB_04: ; RLC H
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Z80_instr_CB_05: ; RLC L
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Z80_instr_CB_06: ; RLC (HL)
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Z80_instr_CB_07: ; RLC A
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Z80_instr_CB_08: ; RRC B
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Z80_instr_CB_09: ; RRC C
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Z80_instr_CB_0A: ; RRC D
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Z80_instr_CB_0B: ; RRC E
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Z80_instr_CB_0C: ; RRC H
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Z80_instr_CB_0D: ; RRC L
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Z80_instr_CB_0E: ; RRC (HL)
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Z80_instr_CB_0F: ; RRC A
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Z80_instr_CB_10: ; RL B
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Z80_instr_CB_11: ; RL C
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Z80_instr_CB_12: ; RL D
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Z80_instr_CB_13: ; RL E
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Z80_instr_CB_14: ; RL H
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Z80_instr_CB_15: ; RL L
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Z80_instr_CB_16: ; RL (HL)
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Z80_instr_CB_17: ; RL A
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Z80_instr_CB_18: ; RR B
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Z80_instr_CB_19: ; RR C
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Z80_instr_CB_1A: ; RR D
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Z80_instr_CB_1B: ; RR E
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Z80_instr_CB_1C: ; RR H
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Z80_instr_CB_1D: ; RR L
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Z80_instr_CB_1E: ; RR (HL)
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Z80_instr_CB_1F: ; RR A
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Z80_instr_CB_20: ; SLA B
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Z80_instr_CB_21: ; SLA C
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Z80_instr_CB_22: ; SLA D
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Z80_instr_CB_23: ; SLA E
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Z80_instr_CB_24: ; SLA H
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Z80_instr_CB_25: ; SLA L
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Z80_instr_CB_26: ; SLA (HL)
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Z80_instr_CB_27: ; SLA A
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Z80_instr_CB_28: ; SRA B
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Z80_instr_CB_29: ; SRA C
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Z80_instr_CB_2A: ; SRA D
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Z80_instr_CB_2B: ; SRA E
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Z80_instr_CB_2C: ; SRA H
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Z80_instr_CB_2D: ; SRA L
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Z80_instr_CB_2E: ; SRA (HL)
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Z80_instr_CB_2F: ; SRA A
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Z80_instr_CB_38: ; SRL B
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Z80_instr_CB_39: ; SRL C
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Z80_instr_CB_3A: ; SRL D
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Z80_instr_CB_3B: ; SRL E
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Z80_instr_CB_3C: ; SRL H
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Z80_instr_CB_3D: ; SRL L
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Z80_instr_CB_3E: ; SRL (HL)
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Z80_instr_CB_3F: ; SRL A
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Z80_instr_DD_09: ; ADD IX,BC
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Z80_instr_DD_19: ; ADD IX,DE
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Z80_instr_DD_21: ; LD IX,nn
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Z80_instr_DD_22: ; LD (nn),IX
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Z80_instr_DD_29: ; ADD IX,IX
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Z80_instr_DD_2A: ; LD IX,(nn)
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Z80_instr_DD_39: ; ADD IX,SP
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Z80_instr_DD_46: ; LD B,(IX+d)
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Z80_instr_DD_4E: ; LD C,(IX+d)
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Z80_instr_DD_56: ; LD D,(IX+d)
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Z80_instr_DD_5E: ; LD E,(IX+d)
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Z80_instr_DD_66: ; LD H,(IX+d)
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Z80_instr_DD_6E: ; LD L,(IX+d)
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Z80_instr_DD_70: ; LD (IX+d),B
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Z80_instr_DD_71: ; LD (IX+d),C
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Z80_instr_DD_72: ; LD (IX+d),D
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Z80_instr_DD_73: ; LD (IX+d),E
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Z80_instr_DD_74: ; LD (IX+d),H
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Z80_instr_DD_75: ; LD (IX+d),L
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Z80_instr_DD_77: ; LD (IX+d),A
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Z80_instr_DD_7E: ; LD A,(IX+d)
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Z80_instr_DD_86: ; ADD A,(IX+d)
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Z80_instr_DD_8E: ; ADC A,(IX+d)
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Z80_instr_DD_96: ; SUB (IX+d)
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Z80_instr_DD_9E: ; SBC (IX+d)
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Z80_instr_DD_A6: ; AND (IX+d)
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Z80_instr_DD_AE: ; XOR (IX+d)
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Z80_instr_DD_B6: ; OR (IX+d)
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Z80_instr_DD_BE: ; CP (IX+d)
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Z80_instr_DD_E3: ; EX (SP),IX
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Z80_instr_DD_F9: ; LD SP,IX
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Z80_instr_ED_40: ; IN B,(C)
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Z80_instr_ED_41: ; OUT (C),B
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Z80_instr_ED_42: ; SBC HL,BC
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Z80_instr_ED_43: ; LD (nn),BC
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Z80_instr_ED_44: ; NEG
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Z80_instr_ED_45: ; RETN
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Z80_instr_ED_48: ; IN C,(C)
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Z80_instr_ED_49: ; OUT (C),C
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Z80_instr_ED_4A: ; ADC HL,BC
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Z80_instr_ED_4B: ; LD BC,(nn)
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Z80_instr_ED_4D: ; RETTI
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Z80_instr_ED_50: ; IN D,(C)
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Z80_instr_ED_51: ; OUT (C),D
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Z80_instr_ED_52: ; SBC HL,DE
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Z80_instr_ED_53: ; LD (nn),DE
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Z80_instr_ED_58: ; IN E,(C)
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Z80_instr_ED_59: ; OUT (C),E
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Z80_instr_ED_5A: ; ADC HL,DE
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Z80_instr_ED_5B: ; LD DE,(nn)
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Z80_instr_ED_60: ; IN H,(C)
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Z80_instr_ED_61: ; OUT (C),H
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Z80_instr_ED_62: ; SBC HL,HL
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Z80_instr_ED_67: ; RRD
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Z80_instr_ED_68: ; IN L,(C)
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Z80_instr_ED_69: ; OUT (C),L
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Z80_instr_ED_6A: ; ADC HL,HL
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Z80_instr_ED_6F: ; RLD
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Z80_instr_ED_72: ; SBC HL,SP
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Z80_instr_ED_73: ; LD (nn),SP
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Z80_instr_ED_78: ; IN A,(C)
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Z80_instr_ED_79: ; OUT (C),A
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Z80_instr_ED_7A: ; ADC HL,SP
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Z80_instr_ED_7B: ; LD SP,(nn)
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Z80_instr_ED_A0: ; LDI
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Z80_instr_ED_A1: ; CPI
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Z80_instr_ED_A2: ; INI
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Z80_instr_ED_A3: ; OUTI
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Z80_instr_ED_A8: ; LDD
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Z80_instr_ED_A9: ; CPD
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Z80_instr_ED_AA: ; IND
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Z80_instr_ED_AB: ; OUTD
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Z80_instr_ED_B0: ; LDIR
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Z80_instr_ED_B1: ; CPIR
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Z80_instr_ED_B2: ; INIR
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Z80_instr_ED_B3: ; OTIR
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Z80_instr_ED_B8: ; LDDR
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Z80_instr_ED_B9: ; CPDR
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Z80_instr_ED_BA: ; INDR
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Z80_instr_ED_BB: ; OTDR
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Z80_instr_FD_09: ; ADD IY,BC
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Z80_instr_FD_19: ; ADD IY,DE
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Z80_instr_FD_21: ; LD IY,nn
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Z80_instr_FD_22: ; LD (nn),IY
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Z80_instr_FD_29: ; ADD IY,IY
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Z80_instr_FD_2A: ; LD IY,(nn)
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Z80_instr_FD_39: ; ADD IY,SP
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Z80_instr_FD_46: ; LD B,(IY+d)
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Z80_instr_FD_4E: ; LD C,(IY+d)
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Z80_instr_FD_56: ; LD D,(IY+d)
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Z80_instr_FD_5E: ; LD E,(IY+d)
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Z80_instr_FD_66: ; LD H,(IY+d)
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Z80_instr_FD_6E: ; LD L,(IY+d)
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Z80_instr_FD_70: ; LD (IY+d),B
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Z80_instr_FD_71: ; LD (IY+d),C
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Z80_instr_FD_72: ; LD (IY+d),D
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Z80_instr_FD_73: ; LD (IY+d),E
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Z80_instr_FD_74: ; LD (IY+d),H
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Z80_instr_FD_75: ; LD (IY+d),L
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Z80_instr_FD_77: ; LD (IY+d),A
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Z80_instr_FD_7E: ; LD A,(IY+d)
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Z80_instr_FD_86: ; ADD A,(IY+d)
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Z80_instr_FD_8E: ; ADC A,(IY+d)
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Z80_instr_FD_96: ; SUB (IY+d)
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Z80_instr_FD_9E: ; SBC (IY+d)
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Z80_instr_FD_A6: ; AND (IY+d)
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Z80_instr_FD_AE: ; XOR (IY+d)
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Z80_instr_FD_B6: ; OR (IY+d)
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Z80_instr_FD_BE: ; CP (IY+d)
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Z80_instr_FD_E3: ; EX (SP),IY
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Z80_instr_FD_F9: ; LD SP,IY
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Z80_instr_DDCB_06: ; RLC (IX+d)
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Z80_instr_DDCB_0E: ; RRC (IX+d)
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Z80_instr_DDCB_16: ; RL (IX+d)
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Z80_instr_DDCB_1E: ; RR (IX+d)
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Z80_instr_DDCB_26: ; SLA (IX+d)
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Z80_instr_DDCB_2E: ; SRA (IX+d)
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Z80_instr_DDCB_3E: ; SRL (IX+d)
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Z80_instr_FDCB_06: ; RLC (IY+d)
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Z80_instr_FDCB_0E: ; RRC (IY+d)
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Z80_instr_FDCB_16: ; RL (IY+d)
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Z80_instr_FDCB_1E: ; RR (IY+d)
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Z80_instr_FDCB_26: ; SLA (IY+d)
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Z80_instr_FDCB_2E: ; SRA (IY+d)
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Z80_instr_FDCB_3E: ; SRL (IY+d)
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jmp ZVM_next ; XXX
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; XXX add 'illegal' instructions
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