feat(kernel): add debounced (glitch-filtered) sense-line reads #5
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The IEC bit loop sampled GPIO with a single register read, so a glitch
on a level-shifted 5V<->3.3V bus could corrupt a bit with no chance to
retry (the loop runs with IRQs off). Add a stable-read filter that only
believes a level change after it holds IEC_DEBOUNCE_US (now 5 us); the
fast path is a single read so tight CLK polls stay cheap. Used across
the receive hot path; the ATN ISR and self-test keep raw reads.
Generated by Clanker
The worker kthread and ATN ISR both modify the DATA line by changing GPIO2's direction (open-drain emulation). On quad-core Pi they run simultaneously on different CPUs, causing their read-modify-write operations on the shared GPFSEL0 register to clobber each other. The ISR's ATN presence-acknowledge could be erased by the worker's ready-for-data release, causing the C64 to see "device not present" and drop LISTEN/UNLISTEN command bytes. Add iec_data_lock spinlock and two synchronized wrappers: - iec_data_assert_sync(): serializes DATA assert - iec_data_release_sync(): serializes DATA release and refuses to release while ATN is asserted, preventing the acknowledge from being undone Convert all worker and ISR DATA accesses to use the _sync() wrappers. Keep raw unconditional helpers for init/exit/self-test (exit must free the bus unconditionally; self-test probes directly). Generated by Clanker 🤖Add row to "Decisions baked into the code" table explaining the DATA line control design: all DATA assert/release operations in the worker and ATN ISR go through iec_data_*_sync() under iec_data_lock to serialize the GPFSEL0 read-modify-write across CPUs. The release wrapper refuses to release while ATN is asserted, preventing the ready-for-data release from erasing the ISR's presence acknowledge — the bug that caused intermittently missed LISTEN/UNLISTEN commands. Init/exit/self-test keep raw unconditional helpers. Generated by Clanker 🤖Checkout
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