Christian Werner
b2e4f9710d
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Adopt the confirmed-working reference's pin assignment so the module runs on that proven wiring: DATA=BCM2 (pin 3), CLK=BCM3 (pin 5), ATN=BCM4 (pin 7). RESET is kept and relocated to BCM17 (pin 11), the pin freed by moving CLK. All five GPIOs stay in bank 0, so the direct-register hot path and ATN IRQ are unchanged -- only the IEC_GPIO_* defines, the device-tree overlay, and the docs/self-test move. DATA/CLK now sit on the ARM I2C pins (GPIO2/3) with the SoC's fixed ~1.8k pull-ups; keep dtparam=i2c_arm off. The bare-board self-test expectation changes from 0x15 to 0x0b accordingly. Generated by Clanker
62 lines
2.8 KiB
Markdown
62 lines
2.8 KiB
Markdown
# Wiring — Pi Zero 2 W ↔ Commodore IEC bus
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PoC listener (printer) interface. Full rationale: PLAN.md §3 and
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`_research/commodore-iec-serial-bus-2026-06-18.md` §1.
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> ⚠️ The Pi GPIO is **3.3 V and NOT 5 V tolerant**. The IEC bus idles at 5 V.
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> A level shifter is **mandatory** — never wire a bus line straight to a Pi pin.
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## Topology
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A single **4-channel bidirectional MOSFET level shifter** (BSS138 + pull-ups,
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the "logic level converter" board) carries all four lines:
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- low side → Pi 3.3 V rail
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- high side → IEC bus 5 V rail
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- **DATA** is the one bidirectional, open-drain-emulated line.
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- **ATN / CLK / RESET** are input-only (Pi always reads them).
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- 100 nF bypass cap across the shifter VCC pins.
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- **Common ground** between Pi GND and IEC pin 2.
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- SRQ (IEC pin 1) left unconnected.
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The shifter is **non-inverting**: bus low (asserted) ⇒ Pi reads LOW.
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## Pin map
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| IEC signal | IEC DIN pin | Pi GPIO (BCM) | Header pin | Direction |
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|------------|-------------|---------------|------------|-----------|
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| ATN | 3 | GPIO 4 | 7 | input (via shifter) |
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| CLK | 4 | GPIO 3 | 5 | input (via shifter) |
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| DATA | 5 | GPIO 2 | 3 | **bidirectional** (via shifter) |
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| RESET | 6 | GPIO 17 | 11 | input (via shifter) |
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| GND | 2 | GND | 6 (or any) | — |
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| SRQ | 1 | — | — | not connected |
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> ℹ️ **DATA (GPIO2) and CLK (GPIO3) are the Pi's ARM I²C pins** and carry the
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> SoC's fixed ~1.8 kΩ pull-ups (benign — DATA is open-drain). Keep
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> `dtparam=i2c_arm` **off** in `/boot/firmware/config.txt` (the default) so I²C
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> does not claim these pins. This layout matches a confirmed-working reference
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> listener.
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## DATA open-drain emulation
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GPIO 2 is never a push-pull driver of the bus. The module flips its direction:
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- **assert** (pull bus low): GPIO 2 = output **LOW** → shifter pulls bus to 0 V.
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- **release / read**: GPIO 2 = **input (Hi-Z)** → bus pull-ups float it to 5 V,
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and GPIO 2 reads the level the *talker* (C64) is driving — this is how bits
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are sampled during receive.
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Logical mapping (handled in `kernel/iec_lines.h`): asserted ⇔ Pi reads LOW.
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## Bring-up checklist (before connecting the C64)
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1. Load the module: `sudo insmod kernel/iec_listener.ko`.
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2. Run the wiring selftest (drives DATA low, releases, reads back; reads sense
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lines) via the `IEC_IOC_SELFTEST` ioctl — expect:
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- DATA reads low while driven, high after release (Hi-Z floats up);
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- ATN / CLK / RESET all released (high) with the C64 powered off.
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3. Meter/LED-check each line for the expected idle-high.
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4. Verify common ground continuity Pi↔IEC pin 2.
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5. Only then connect the C64 and try `OPEN 1,4 : CLOSE 1`.
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